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L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
The address space of the L64118 is partitioned into the following areas:
CPU/Peripheral
This address space contains the control and status registers for the
CPU and core building blocks.
Conguration Register Space
The space contains registers that dene the conguration of each
peripheral on the PBus. It is partitioned into 1 Kbyte segments,
where each segment corresponds to the Conguration register entry
Attribute Register Space
The Attribute register space contains the Attribute register 0 for each
peripheral on the PBus. This space is partitioned into 1 Kbyte
segments, where each segment corresponds to the Attribute register
entry for each PBus component. See
Table 3. Internal I/O
The internal I/O space contains I/O registers and functions for each
peripheral on the PBus. It is partitioned into 256 4 Kbyte segments,
where each segment corresponds to an I/O entry for a PBus
External ROM
External ROM contains the operating system, user’s application
programs (
kseg0), conguration code, and initialized data (kseg1).
External space for the EBus
The external space is used for user-dened external memory and
external devices residing on the EBus. It is divided into three
subspaces, each one supporting devices with a different width (8, 16,
32 bits).
Primary SDRAM
The lowest 2/8/16 Mbytes of addressable space are mapped to the
external SDRAM through the internal SDRAM controller. See
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