
58
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
SBA[0]
SDRAM Bank Select 0
Output
6
–
SBA[1]
SDRAM Bank Select 1
Output
6
–
SBD[15:0]
SDRAM Data Bus
Bidirectional
6
–
SC0_C4
SmartCard 0 C4
Bidirectional
(open drain)
6–
–
SC0_C8
SmartCard 0 C8
Bidirectional
(open drain)
6–
–
SC0_CLK
GPIO33
SmartCard 0 Clock
General-Purpose I/O 33
Output
Bidirectional
6
––
SC0_DETECT
GPIO31
SmartCard 0 Detect
General-Purpose I/O 31
Input
Bidirectional
4
HIGH
–
SC0_I/O
SmartCard 0 Data
Bidirectional
(open drain)
6–
–
SC0_RSTn
GPIO30
SmartCard 0 Reset
General-Purpose I/O 30
Output
Bidirectional
4
LOW
–
SC0_VCC_ENn
GPIO32
SmartCard 0 VCC Enable
General-Purpose I/O 32
Output
Bidirectional
4
LOW
–
SC0_VPP_ENn
GPIO34
SmartCard 0 VPP Enable
General-Purpose I/O 34
Output
Bidirectional
4
LOW
–
SC1_CLK
GPIO38
SmartCard 1 Clock
General-Purpose I/O 38
Output
Bidirectional
6
––
SC1_DETECT
GPIO36
SmartCard 1 Detect
General-Purpose I/O 36
Input
Bidirectional
–
4
HIGH
–
SC1_I/O
SmartCard 1 Data
Bidirectional
(open drain)
6–
–
SC1_RSTn
GPIO35
SmartCard 1 Reset
General-Purpose I/O 35
Output
Bidirectional
4
LOW
–
SC1_VCC_ENn
GPIO37
SmartCard 1 VCC Enable
General-Purpose I/O 37
Output
Bidirectional
4
LOW
–
SC1_VPP_ENn
GPIO39
SmartCard 1 VPP Enable
General-Purpose I/O 39
Output
Bidirectional
4
LOW
–
Table 17
Pin Description Summary (Cont.)
Mnemonic
Description
Type1
Drive
(mA)
Active2
Pull-Up/
Down
118bds Page 58 Wednesday, February 3, 1999 12:37 PM