- 您现在的位置：买卖IC网 > Datasheet目录336 > LC4064ZC-EV (Lattice Semiconductor Corporation)BOARD EVAL FOR ISPMACH 4064ZC Datasheet资料下载
参数资料
| 型号： | LC4064ZC-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 11/99页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ISPMACH 4064ZC |
| 标准包装： | 1 |
| 系列： | ispMACH®4000Z |
| 类型： | CPLD |
| 适用于相关产品： | LC4064ZC |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | LC4064ZCEV |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页
Lattice Semiconductor
Table 10. ORP Combinations for I/O Blocks with 12 I/Os
ispMACH 4000V/B/C/Z Family Data Sheet
I/O Cell
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
Available Macrocells
M0, M1, M2, M3, M4, M5, M6, M7
M1, M2, M3, M4, M5, M6, M7, M8
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M5, M6, M7, M8, M9, M10, M11, M12
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M9, M10, M11, M12, M13, M14, M15, M0
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M13, M14, M15, M0, M1, M2, M3, M4
M14, M15, M0, M1, M2, M3, M4, M5
ORP Bypass and Fast Output Multiplexers
The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the
ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also
allows the register output to bypass the ORP to achieve faster t CO .
Output Enable Routing Multiplexers
The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.
I/O Cell
The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus
maintenance circuitry. Figure 8 details the I/O cell.
Figure 8. I/O Cell
GOE 0
GOE 1
GOE 2
GOE 3
From ORP
VCC
V CCO
V CCO
From ORP
*
*
*
To Macrocell
To GRP
*Global fuses
Each output supports a variety of output standards dependent on the V CCO supplied to its I/O bank. Outputs can
also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the V CCO supplied to its I/O bank. The I/O standards supported are:
11
相关PDF资料 |
PDF描述 |
|---|---|
| LCMXO2280C-C-EVN | BOARD CONTROL EVAL MACHXO |
| LDB100-024SW | LED POWER SUPPLY 24V 0-4A 100W |
| LDB150-048SW | LED POWER SUPPLY 24V-48V 3.125A |
| LDB200-048SW | LED POWER SUPPLY 24V-48V 4.2A |
| LDB75-048SW | LED POWER SUPPLY 24V-48V 1.56A |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LC4064ZE4MN100C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4064ZE4MN100CES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4064ZE4MN100I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4064ZE4MN100IES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4064ZE4MN144C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
发布紧急采购，3分钟左右您将得到回复。