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| 型号： | LC4064ZC-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 7/99页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ISPMACH 4064ZC |
| 标准包装： | 1 |
| 系列： | ispMACH®4000Z |
| 类型： | CPLD |
| 适用于相关产品： | LC4064ZC |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | LC4064ZCEV |
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Lattice Semiconductor
Table 5. Product Term Expansion Capability
ispMACH 4000V/B/C/Z Family Data Sheet
Expansion
Chains
Chain-0
Chain-1
Chain-2
Chain-3
Macrocells Associated with Expansion Chain
(with Wrap Around)
M0 M4 M8 M12 M0
M1 M5 M9 M13 M1
M2 M6 M10 M14 M2
M3 M7 M11 M15 M3
Max PT/
Macrocell
75
80
75
70
Every time the super cluster allocator is used, there is an incremental delay of t EXP . When the super cluster alloca-
tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-
ter is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-
grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.
Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input
from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable
delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.
Figure 5. Macrocell
Power-up
Initialization
Shared PT Initialization
PT Initialization (optional)
PT Initialization/CE (optional)
Delay
From I/O Cell
From Logic Allocator
R
D/T/L
P
Q
To ORP
To GRP
CE
Single PT
Block CLK0
Block CLK1
Block CLK2
Block CLK3
PT Clock (optional)
Shared PT Clock
Enhanced Clock Multiplexer
The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:
? Block CLK0
? Block CLK1
7
相关PDF资料 |
PDF描述 |
|---|---|
| LCMXO2280C-C-EVN | BOARD CONTROL EVAL MACHXO |
| LDB100-024SW | LED POWER SUPPLY 24V 0-4A 100W |
| LDB150-048SW | LED POWER SUPPLY 24V-48V 3.125A |
| LDB200-048SW | LED POWER SUPPLY 24V-48V 4.2A |
| LDB75-048SW | LED POWER SUPPLY 24V-48V 1.56A |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LC4064ZE4MN100C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4064ZE4MN100CES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4064ZE4MN100I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4064ZE4MN100IES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4064ZE4MN144C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
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