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参数资料
| 型号： | LMK04033BISQE/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 17/65页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CONDITIONER PREC 48LLP |
| 标准包装： | 1 |
| 系列： | PowerWise® |
| 类型： | 时钟调节器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS，LVDS，2VPECL，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.16GHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-LLP（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 1275 (CN2011-ZH PDF) |
| 其它名称： | LMK04033BISQEDKR |
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SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
FEATURES
System Architecture
The cascaded PLL architecture of the LMK040xx was chosen to provide the lowest jitter performance over the
widest range of output frequencies and phase noise offset frequencies. The first stage PLL (PLL1) is used in
conjunction with an external reference clock and an external VCXO to provide a frequency accurate, low phase
noise reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow
loop bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the
same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated
along its path or from other circuits. The “cleaned” reference clock frequency accuracy is combined with the low
phase noise of an external VCXO to provide the reference input to PLL2. The low phase noise reference
provided to PLL2 allows it to use wider loop bandwidths (50 kHz to 200 kHz). The chosen loop bandwidth for
PLL2 should take best advantage of the superior high offset frequency phase noise profile of the internal VCO
and the good low offset frequency phase noise of the reference VCXO for PLL2. Ultra low jitter is achieved by
allowing the external VCXO’s phase noise to dominate the final output phase noise at low offset frequencies and
the internal VCO’s phase noise to dominate the final output phase noise at high offset frequencies. This results in
best overall phase noise and jitter performance.
Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
The LMK040xx has two LVDS/LVPECL/LVCMOS compatible reference clock inputs for PLL1, CLKin0 and
CLKin1. The selection of the preferred input may be fixed to either CLKin0 or CLKin1, or may be configured to
employ one of two automatic switching modes when redundant clock signals are present. The PLL1 reference
clock input buffers may also be individually configured as either a CMOS buffered input or a bipolar buffered
input.
PLL1 CLKinX (X=0,1) LOSS OF SIGNAL (LOS)
When either of the two auto-switching modes is selected for the reference clock input mode, the signal status of
the selected reference clock input is indicated by the state of the CLKinX_LOS (loss-of-signal) output. These
outputs may be configured as either CMOS (active HIGH on loss-of-signal), NMOS open-drain or PMOS open-
drain. If PLL1 was originally locked and then both reference clocks go away, then the frequency accuracy of the
LMK04000 device will be set by the absolute tuning range of the VCXO used on PLL1. The absolute tuning
range of the VCXO can be determined by multiplying its' tuning constant by the charge pump voltage.
Integrated Loop Filter Poles
The LMK040xx features programmable 3rd and 4th order loop filter poles for PLL2. When enabled, internal
resistors and capacitor values may be selected from a fixed range of values to achieve either 3rd or 4th order
loop filter response. These programmable components compliment external components mounted near the chip.
Clock Distribution
The LMK040xx features a clock distribution block with a minimum of five outputs that are a mixture of LVPECL,
2VPECL, LVDS, and LVCMOS. The exact combination is determined by the part number. The 2VPECL is a
National Semiconductor proprietary configuration that produces a 2 Vpp differential swing for compatibility with
many data converters. More than five outputs may be available for device versions that offer dual LVCMOS
outputs.
CLKout Divide (CLKoutX_DIV, X = 0 to 4)
Each individual clock distribution channel includes a channel divider. The range of divide values is 2 to 510, in
steps of 2. “Bypass” mode operates as a divide-by-1.
CLKout Delay (CLKoutX_DLY, X = 0 to 4)
Each individual clock distribution channel includes a delay adjustment. Clock output delay registers
(CLKoutX_DLY) support a nominal 150 ps step size and range from 0 to 2250 ps of total delay.
24
Copyright 2008–2011, Texas Instruments Incorporated
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LMK04033BISQX | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
| LMK04033BISQX/NOPB | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| LMK04100 | 制造商:TI 制造商全称:Texas Instruments 功能描述:LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs |
| LMK04100EVAL/NOPB | 功能描述:时钟和定时器开发工具 LMK04100 Eval Mod RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| LMK04100SQ/NOPB | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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