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参数资料
| 型号： | LMK04033BISQE/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 20/65页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CONDITIONER PREC 48LLP |
| 标准包装： | 1 |
| 系列： | PowerWise® |
| 类型： | 时钟调节器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS，LVDS，2VPECL，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.16GHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-LLP（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 1275 (CN2011-ZH PDF) |
| 其它名称： | LMK04033BISQEDKR |
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tCES
tCS
D27
D26
D25
D24
tCH
tCWH
tCWL
D23
D0
A3
A2
A1
A0
MSB
LSB
DATAuWire
CLKuWire
LEuWire
tES
tEWH
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Fout
The buffered output of the internal VCO is available at the Fout pin. This is a single-ended output (sinusoid).
Each time the PLL2_N counter value is updated via the uWire interface, an internal algorithm is triggered that
optimizes the VCO performance.
Digital Lock Detect 1 Bypass
The VCO coarse tuning algorithm requires a stable OSCin clock (reference clock to PLL2) to frequency calibrate
the internal VCO correctly. In order to ensure a stable OSCin clock, the first PLL must achieve lock status. A
digital lock detect is used in PLL1 to monitor its lock status. After lock is achieved by PLL1, the coarse tuning
circuitry is enabled and frequency calibration for the internal VCO begins.
The (DLD_BYP) pin is provided to allow an external bypass cap to be connected to the digital lock detect 1. This
capacitor will eliminate potential glitches at initial startup of PLL1 due to unknown phase relationships between
the Ncntr1 and Rcntr1.
Bias
Proper bypassing of this pin by a 1 F capacitor connected to VCC is important for low noise performance.
General Programming Information
LMK040xx devices are programmed using several 32-bit registers. Each register consists of a 4-bit address field
and 28-bit data field. The address field is formed by bits 0 through 3 (LSBs) and the data field is formed by bits 4
through 31 (MSBs). The contents of each register are clocked in MSB first (bit 31), and the LSB (bit 0) last.
During programming, the LE signal should be held LOW. The serial data is clocked in on the rising edge of the
CLK signal. After the LSB (bit 0) is clocked in the LE signal should be toggled LOW-to-HIGH-to-LOW to latch the
contents into the register selected in the address field. Registers R0-R4, R7, and R8-R15 must be programmed
in order to achieve proper device operation. Figure 12 illustrates the serial data timing sequence.
Figure 12. uWire Timing Diagram
To achieve proper frequency calibration, the OSCin port must be driven with a valid signal before programming
Register 15. Changes to PLL2_R Counter or the OSCin port signal require Register 15 to be reloaded in order to
activate the frequency calibration process.
Recommended Programming Sequence
The recommended programming sequence involves programming R7 with the reset bit set to 1 (Reg. 7, bit 4) to
ensure the device is in a default state. If R7 is programmed again, the reset bit should be set to 0. Registers are
programmed in order with R15 being the last register programmed. An example programming sequence is
shown below:
Program R7 with the RESET bit = 1 (b4 = 1). This ensures that the device is configured with default settings.
When RESET = 1, all other R7 bits are ignored.
–
- If R7 is programmed again during the initial configuration of the device, the RESET bit should be cleared
(b4 = 0)
Program R0 through R4 as necessary to configure the clock outputs as desired. These registers configure
clock channel functions such as the channel multiplexer output selection, divide value, delay value, and
enable/disable bit.
Copyright 2008–2011, Texas Instruments Incorporated
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LMK04033BISQX | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
| LMK04033BISQX/NOPB | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| LMK04100 | 制造商:TI 制造商全称:Texas Instruments 功能描述:LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs |
| LMK04100EVAL/NOPB | 功能描述:时钟和定时器开发工具 LMK04100 Eval Mod RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| LMK04100SQ/NOPB | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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