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参数资料
| 型号： | LMK04033BISQE/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 26/65页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CONDITIONER PREC 48LLP |
| 标准包装： | 1 |
| 系列： | PowerWise® |
| 类型： | 时钟调节器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS，LVDS，2VPECL，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.16GHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-LLP（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 1275 (CN2011-ZH PDF) |
| 其它名称： | LMK04033BISQEDKR |
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SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Register R0 To R4
Registers R0 through R4 control the five clock outputs. Register R0 controls CLKout0, Register R1 controls
CLKout1, and so on. Aside from this, the functions of the bits in these registers are identical. The X in
CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be
from 0 to 4.
CLKoutX_DIV: Clock Channel Divide Registers
Each of the five clock output channels (0 though 4) has a dedicated 8-bit divider followed by a fixed divide by 2
that is used to generate even integer related versions of the distribution path clock frequency (VCO Divider
output). If the VCO Divider value is even then the Channel Divider may be bypassed (See CLK Output Mux),
giving an effective divisor of 1 while preserving a 50% duty cycle output waveform.
Table 5. CLKoutX_DIV: Clock Channel Divide Values
CLKoutX_DIV [ 7:0 ]
Total Divide Value
b7
b6
b5
b4
b3
b2
b1
b0
0
invalid
0
1
2
0
1
0
4
0
1
6
0
1
0
8
0
1
0
1
10
-
--
-
1
510
EN_CLKoutX: Clock Channel Output Enable
Each Clock Output Channel may be either enabled or disabled via the Clock Output Enable control bits. Each
output enable control bit is gated with the Global Output Enable input pin (GOE) and Global Output Enable bit
(EN_CLKout_Global). The GOE pin provides an internal pull-up so that if it is unterminated externally, the clock
output states are determined by the Clock Output Enable Register bits. All clock outputs can be set to the low
state simultaneously if the GOE pin is pulled low by an external signal. If EN_CLKout_Global is programmed to 0
all outputs are turned off. If both GOE and EN_CLKout_Global are low the clock outputs are turned off.
Table 6. EN_CLKoutX: Clock Channel Output Enable Control Bits
BIT NAME
BIT = 1
BIT = 0
DEFAULT
EN_CLKout0
ON
OFF
EN_CLKout1
ON
OFF
EN_CLKout2
ON
OFF
ON
EN_CLKout3
ON
OFF
EN_CLKout4
ON
OFF
EN_CLKout_Global
According to individual channel
All EN_CLKout X = OFF
-
settings
Note the default state of CLKout2 is ON after power on or RESET assertion. The nominal frequency is 62 MHz
(LMK040x1) or 81 MHz (LMK040x3). This is based on a channel divide value of 12 and default VCO_DIV value
of 2. If an active CLKout2 at power on is inappropriate for the user’s application, the following method can be
employed to shut off CLKout2 during system initialization:
When the device is powered on, holding the GOE pin LOW will disable all clock outputs. The device can be
programmed while the GOE is held LOW. The state of CLKout2 can be altered during device programming
according to the user’s specific application needs. After device configuration is complete, the GOE pin should
be set HIGH to enable the active clock channels.
32
Copyright 2008–2011, Texas Instruments Incorporated
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| LMK04033BISQX/NOPB | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| LMK04100 | 制造商:TI 制造商全称:Texas Instruments 功能描述:LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs |
| LMK04100EVAL/NOPB | 功能描述:时钟和定时器开发工具 LMK04100 Eval Mod RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| LMK04100SQ/NOPB | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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