参数资料
| 型号： | LT1977IFE#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1.5A 16TSSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.2 V ~ 54 V |
| 输入电压： | 3.3 V ~ 60 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-TSSOP-EP |
LT1977
APPLICATIO S I FOR ATIO
and Soft-Start Current graphs in Typical Performance
LT1977
SW 2
V OUT
Characteristics).
SOFT-START
C SS
9
C1
Frequency foldback is used to control power dissipation in
both the IC and in the external diode and inductor during
short-circuit conditions. A shorted output requires the
500kHz
OSCILLATOR
FOLDBACK
DETECT
R1
switching regulator to operate at very low duty cycles. As
a result the average current through the diode and induc-
ERROR
AMP
FB
12
R2
tor is equal to the short-circuit current limit of the switch
(typically 2A for the LT1977). Minimum switch on time
limitations would prevent the switcher from operating at a
1.25V
sufficiently low duty cycle if switching frequency were
maintained at 500kHz, so frequency is reduced by about
Table 2
V C
Figure 2. Feedback Network
11
1977 F02
4:1 when the FB pin voltage drops below 0.4V (see
Frequency Foldback graph). In addition, if the current in
the switch exceeds 1.5 times the current limitations speci-
fied by the V C pin, due to minimum switch on time, the
LT1977 will skip the next switch cycle. As the feedback
voltage rises, the switching frequency increases to 500kHz
OUTPUT
R1
OUTPUT
with 0.95V on the FB pin. During frequency foldback,
VOLTAGE
(V)
2.5
3
3.3
5
6
8
10
12
R2
(k ? , 1%)
100
100
100
100
100
100
100
100
NEAREST (1%)
(k ? )
100
140
165
300
383
536
698
866
ERROR
(%)
0
0
0.38
0
0.63
– 0.63
– 0.25
0.63
external synchronization is disabled to prevent interfer-
ence with foldback operation. Frequency foldback does
not affect operation during normal load conditions.
In addition to lowering switching frequency the soft-start
ramp rate is also affected by the feedback voltage. Large
capacitive loads or high input voltages can cause a high
input current surge during start-up. The soft-start func-
tion reduces input current surge by regulating switch
current via the V C pin to maintain a constant voltage ramp
rate (dV/dt) at the output. A capacitor (C1 in Figure 2) from
50nA FB pin input current. The suggested value for the
output divider resistor (see Figure 2) from FB to ground
(R2) is 100k or less. A formula for R1 is shown below. A
table of standard 1% values is shown in Table 2 for
common output voltages.
the C SS pin to the output determines the maximum output
dV/dt. When the feedback voltage is below 0.4V, the V C pin
will rise, resulting in an increase in switch current and
output voltage. If the dV/dt of the output causes the current
through the C SS capacitor to exceed I CSS the V C voltage is
R 1 = R 2 ?
V OUT – 1 . 25
1 . 25 + R 2 ? 50 nA
reduced resulting in a constant dV/dt at the output. As the
feedback voltage increases I CSS increases, resulting in an
increased dV/dt until the soft-start function is defeated
More Than Just Voltage Feedback
The FB pin is used for more than just output voltage
sensing. It also reduces switching frequency and con-
trols the soft-start voltage ramp rate when output voltage
with 0.9V present at the FB pin. The soft-start function
does not affect operation during normal load conditions.
However, if a momentary short (brown out condition) is
present at the output which causes the FB voltage to drop
below 0.9V, the soft-start circuitry will become active.
is below the regulated level (see the Frequency Foldback
1977fa
10
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