参数资料
| 型号： | LT1977IFE#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1.5A 16TSSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.2 V ~ 54 V |
| 输入电压： | 3.3 V ~ 60 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-TSSOP-EP |
LT1977
APPLICATIO S I FOR ATIO
low value such that the current doesn’t continue to ratchet
higher. When the FB pin voltage is abnormally low thereby
indicating some sort of short-circuit condition, the oscil-
C CSS = 1000pF
lator frequency will be reduced. Oscillator frequency is
reduced by a factor of 4 when the FB pin voltage is below
0.4V and increases linearly to its typical value of 500kHz at
a FB voltage of 0.95V (see Typical Performance Character-
V OUT
1V/DIV
C CSS = 0.01 μ F
C CSS = 0.1 μ F
istics). In addition, if the current in the switch exceeds 1.5
? I PK current demanded by the V C pin, the LT1977 will skip
the next on cycle effectively reducing the oscillator fre-
quency by a factor of 2. These oscillator frequency reduc-
tions during short-circuit conditions allow the LT1977 to
V IN = 12V
V OUT = 3.3V
1ms/DIV
Figure 4. V OUT dV/dt
1977 F04
maintain current control.
capacitor charged to the proper voltage while minimizing
? V ? ( I BIASS + I FB + I S )
( )
I IN ( AVG ) ? I VINS + I SHDN + ? OUT ?
= CSS
SOFT-START
For applications where [V IN /(V OUT + V F )] ratios > 10 or
large input surge currents can’t be tolerated, the LT1977
soft-start feature should be used to control the output
capacitor charge rate during start-up, or during recovery
from an output short circuit thereby adding additional
control over peak inductor current. The soft-start function
limits the switch current via the V C pin to maintain a
constant voltage ramp rate (dV/dt) at the output capacitor.
A capacitor (C1 in Figure 2) from the C SS pin to the
regulated output voltage determines the output voltage
ramp rate. When the current through the C SS capacitor
exceeds the C SS threshold (I CSS ), the voltage ramp of the
output capacitor is limited by reducing the V C pin voltage.
The C SS threshold is proportional to the FB voltage (see
Typical Performance Characteristics) and is defeated for
FB voltages greater than 0.9V (typical). The output dV/dt
can be approximated by:
dV I
dt C SS
but actual values will vary due to start-up load conditions,
compensation values and output capacitor selection.
Burst Mode OPERATION
To enhance efficiency at light loads, the LT1977 automati-
cally switches to Burst Mode operation (see Typical
the input quiescent current. During Burst Mode opera-
tion, the LT1977 delivers short bursts of current to the
output capacitor followed by sleep periods where the
output power is delivered to the load by the output
capacitor. In addition, V IN and BIAS quiescent currents
are reduced to typically 45 μ A and 110 μ A respectively
during the sleep time. As the load current decreases
towards a no load condition, the percentage of time that
the LT1977 operates in sleep mode increases and the
average input current is greatly reduced resulting in
higher efficiency.
The minimum average input current depends on the V IN to
V OUT ratio, V C frequency compensation, feedback divider
network and Schottky diode leakage. It can be approxi-
mated by the following equation:
? V IN ? η
where:
I VINS = input pin current in sleep mode
V OUT = output voltage
V IN = input voltage
I BIASS = BIAS pin current in sleep mode
I FB = feedback network current
I S = catch diode reverse leakage at V OUT
η = low current efficiency (non Burst Mode operation)
Performance Characteristics) which keeps the output
1977fa
15
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