参数资料
| 型号： | LT1977IFE#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1.5A 16TSSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.2 V ~ 54 V |
| 输入电压： | 3.3 V ~ 60 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-TSSOP-EP |
LT1977
TYPICAL PERFOR A CE CHARACTERISTICS
Dropout Operation
Dropout Operation
Burst Mode Operation
4.0
3.5
V OUT = 3.3V
BOOST DIODE = DIODES INC B1100
6
5
V OUT = 5V
BOOST DIODE = DIODES INC B1100
3.0 LOAD CURRENT = 250mA
2.5
4
LOAD CURRENT = 250mA
V OUT
20mV/DIV
2.0
1.5
LOAD CURRENT = 1.25A
3
LOAD CURRENT = 1.25mA
I SW
500mA/DIV
2
1.0
0.5
0
2
2.5
3
3.5
4
4.5
1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
V IN = 12V
V OUT = 3.3V
I Q = 100 μ A
5ms/DIV
1977 G14
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
V OUT
20mV/DIV
Burst Mode Operation
1977 G23
V OUT
50mV/DIV
No Load 1A Step Response
1977 G24
V OUT
50mV/DIV
Step Response
I OUT
I SW
500mA/DIV
I OUT
500mA/DIV
500mA/DIV
V IN = 12V
V OUT = 3.3V
I Q = 100 μ A
2 μ s/DIV
1977 G15
V IN = 12V
V OUT = 3.3V
C OUT = 100 μ F
I DC = 0mA
500 μ s/DIV
1977 G17
V IN = 12V
V OUT = 3.3V
C OUT = 100 μ F
I DC = 350mA
500 μ s/DIV
1977 G18
PI FU CTIO S
NC (Pins 1, 3, 5): No Connection.
SW (Pin 2): The SW pin is the emitter of the on-chip power
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the SW pin
negative during switch off time. Negative voltage is clamped
with the external catch diode. Maximum negative switch
voltage allowed is –0.8V.
V IN (Pin 4): This is the collector of the on-chip power NPN
switch. V IN powers the internal control circuitry when a
voltage on the BIAS pin is not present. High di/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the V IN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the V CE voltage across the internal NPN.
6
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.2 ? FET
structure.
C T (Pin 7): A capacitor on the C T pin determines the amount
of delay time between the PGFB pin exceeding its thresh-
old (V PGFB ) and the PG pin set to a high impedance state.
When the PGFB pin rises above V PGFB , current is sourced
from the C T pin into the external capacitor. When the volt-
age on the external capacitor reaches an internal clamp
(V CT ), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = C CT ? V CT /I CT . If the
1977fa
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