参数资料
型号: LT3437EFE#PBF
厂商: Linear Technology
文件页数: 17/28页
文件大小: 0K
描述: IC REG BUCK ADJ 0.5A 16TSSOP
标准包装: 95
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.25 V ~ 54 V
输入电压: 3.3 V ~ 60 V
PWM 型: 电流模式,混合
频率 - 开关: 200kHz
电流 - 输出: 500mA
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
供应商设备封装: 16-TSSOP-EP
LT3437
APPLICATIO S I FOR ATIO
Burst Mode OPERATION
To enhance efficiency at light loads, the LT3437 automati-
cally switches to Burst Mode operation which keeps the
output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst
Mode operation, the LT3437 delivers short bursts of
current to the output capacitor followed by sleep periods
where the output power is delivered to the load by the
200
180
160
140
120
100
80
60
40
V OUT = 3.3V
output capacitor. In addition, V IN and BIAS quiescent
currents are reduced to typically 45 μ A and 110 μ A, respec-
20
0
0
10
20
30 40
50
60
70
80
tively, during the sleep time. As the load current decreases
towards a no load condition, the percentage of time that
INPUT VOLTAGE (V)
3435 F05
the LT3437 operates in sleep mode increases and the
average input current is greatly reduced, resulting in
higher efficiency.
The minimum average input current depends on the V IN to
V OUT ratio, V C frequency compensation, feedback divider
network and Schottky diode leakage. It can be approxi-
Figure 5. I Q vs V IN
During the sleep portion of the Burst Mode cycle, the V C
pin voltage is held just below the level needed for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
sient response waveforms.
? V ? ( I BIASS + I FB + I S
()
I IN ( AVG ) ? I VINS + I SHDN + ? OUT ?
mated by the following equation:
? V IN ? η
where
)
If Burst Mode operation is undesirable, it can be defeated
by placing 2V or greater on the SYNC pin. When Burst
Mode operation is defeated, output ripple at light loads will
be reduced at the expense of light load efficiency.
? 3 . 3 ? ( 110 μ A + 12 . 5 μ A + 0.. 5 μ A )
? 12 ? ?
( 0 . 8 )
I VINS = input pin current in sleep mode
V OUT = output voltage
V IN = input voltage
I BIASS = BIAS pin current in sleep mode
I FB = feedback network current
I S = catch diode reverse leakage at V OUT
η = low current efficiency (non Burst Mode operation)
Example: For V OUT = 3.3V, V IN = 12V
I IN ( AVG ) ? 45 μ A + 5 μ A + ?
= 45 μ A + 5 μ A + 42 μ A = 92 μ A
CATCH DIODE
The catch diode carries load current during the SW off
time. The average diode current is therefore dependent on
the switch duty cycle. At high input to output voltage
ratios, the diode conducts most of the time. As the ratio
approaches unity, the diode conducts only a small fraction
of the time. The most stressful condition for the diode is
when the output is short circuited. Under this condition,
the diode must safely handle I PEAK at maximum duty cycle.
To maximize high and low load current efficiency, a fast
switching diode with low forward drop and low reverse
leakage should be used. Low reverse leakage is critical to
maximize low current efficiency since its value over tem-
perature can potentially exceed the magnitude of the
LT3437 supply current. Low forward drop is critical for
high current efficiency since the loss is proportional to
forward drop.
3437fc
17
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