参数资料
型号: LT3437EFE#PBF
厂商: Linear Technology
文件页数: 23/28页
文件大小: 0K
描述: IC REG BUCK ADJ 0.5A 16TSSOP
标准包装: 95
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.25 V ~ 54 V
输入电压: 3.3 V ~ 60 V
PWM 型: 电流模式,混合
频率 - 开关: 200kHz
电流 - 输出: 500mA
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
供应商设备封装: 16-TSSOP-EP
LT3437
APPLICATIO S I FOR ATIO
increase in internal dissipation is of insufficient time dura-
tion to raise die temperature significantly.
A second consideration is controllability. A potential limi-
tation occurs with a high step-down ratio of V IN to V OUT ,
as this requires a correspondingly narrow minimum switch
on time. An approximate expression for this (assuming
continuous mode operation) is given as follows:
t ON(MIN) = (V OUT + V F )/V IN (f OSC )
where:
V IN = input voltage
V OUT = output voltage
V F = Schottky diode forward drop
f OSC = switching frequency
A potential controllability problem arises if the LT3437 is
called upon to produce an on time shorter than it is able to
produce. Feedback loop action will lower, then reduce, the
V C control voltage to the point where some sort of cycle-
skipping or Burst Mode behavior is exhibited.
In summary:
1. Be aware that the simultaneous requirements of high
V IN , high I OUT and high f OSC may not be achievable in
practice due to internal dissipation. The Thermal Con-
siderations section offers a basis to estimate internal
power. In questionable cases, a prototype supply should
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high V IN , low V OUT
and high f OSC can result in an unacceptably short mini-
mum switch on time. Cycle skipping and/or Burst Mode
behavior will result causing an increase in output volt-
age ripple while maintaining the correct output voltage.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits. Read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/or
catch diode, and connecting the V C compensation to a
ground track carrying significant switch current. In addi-
tion, the theoretical analysis considers only first order
non-ideal component behavior. For these reasons, it is
important that a final stability check is made with produc-
tion layout and components.
The LT3437 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 10.
The LT3437 can be considered as two g m blocks, the error
amplifier and the power stage.
Figure 11 shows the overall loop response. At the V C pin,
the frequency compensation components used are:
R C = 25k, C C = 1500pF and C F = 330pF. The output
capacitor used is a 100 μ F, 10V tantalum capacitor with
typical ESR of 100m ? .
The ESR of the tantalum output capacitor provides a useful
zero in the loop frequency response for maintaining stabil-
ity. This ESR, however, contributes significantly to the
ripple voltage at the output (see Output Ripple Voltage in
the Applications Information section). It is possible to
reduce capacitor size and output ripple voltage by replac-
ing the tantalum output capacitor with a ceramic output
capacitor because of its very low ESR. The zero provided
by the tantalum output capacitor must now be reinserted
back into the loop. Alternatively, there may be cases
where, even with the tantalum output capacitor, an addi-
tional zero is required in the loop to increase phase margin
for improved transient response.
3437fc
23
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