LTC2411
27
1%. Such a specification can also be easily achieved by an
external clock. When relatively stable resistors (50ppm/
°C)
are used for the external source impedance seen by REF+
and REF–, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(
±10nA max), results in a small gain error. A 100 source
resistance will create a 0.05
V typical and 0.5V maxi-
mum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2411 can pro-
duce up to 7.5 readings per second with a notch frequency
of 60Hz (FO = LOW) and 6.25 readings per second with a
notch frequency of 50Hz (FO = HIGH). The actual output
data rate will depend upon the length of the sleep and data
output phases which are controlled by the user and which
can be made insignificantly short. When operated with an
external conversion clock (FO connected to an external
oscillator), the LTC2411 output data rate can be increased
as desired. The duration of the conversion phase is 20510/
fEOSC. If fEOSC = 153600Hz, the converter behaves as if the
internal oscillator is used and the notch is set at 60Hz.
There is no significant difference in the LTC2411 perfor-
mance between these two operation modes.
An increase in fEOSC over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mance degradation can be substantially reduced by rely-
ing upon the LTC2411’s exceptional common mode
rejection and by carefully eliminating common mode to
APPLICATIO S I FOR ATIO
WU
UU
OUTPUT DATA RATE (READINGS/SEC)
0
–120
OFFSET
ERROR
(ppm
OF
V
REF
)
–80
–40
0
60 70 80 90
120
2411 F20
10 20 30 40 50
100
40
80
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
TA = 85°C
TA = 25°C
Figure 20. Offset Error vs Output Data Rate and Temperature
differential mode conversion sources in the input circuit.
The user should avoid single-ended input filters and
should maintain a very high degree of matching and
symmetry in the circuits driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor-
mance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
the external source resistance upon the LTC2411 typical
performance can be inferred from Figures 13, 14 and 17 in
which the horizontal axis is scaled by 153600/fEOSC.
Third, an increase in the frequency of the external oscilla-
tor above 460800Hz (a more than 3
×increaseintheoutput
data rate) will start to decrease the effectiveness of the
internal autocalibration circuits. This will result in a progres-
sive degradation in the converter accuracy and linearity.
Typical measured performance curves for output data rates
up to 100 readings per second are shown in Figures 20 to
27. In order to obtain the highest possible level of accuracy
from this converter at output data rates above 20 readings
per second, the user is advised to maximize the power
supply voltage used and to limit the maximum ambient
operating temperature. In certain circumstances, a reduc-
tion of the differential reference voltage may be beneficial.