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LTC2411
11
CONVERTER OPERATION
Converter Operation Cycle
The LTC2411 is a low power, delta-sigma analog-to-digital
converter with an easy to use 3-wire serial interface (see
Figure 1). Its operation is made up of three states. The
converter operating cycle begins with the conversion, fol-
lowed by the low power sleep state and ends with the data
output (see Figure 2). The 3-wire interface consists of serial
data output (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2411 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced by
an order of magnitude. The part remains in the sleep state
as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data
is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 32 bits are read out
of the ADC or when CS is brought HIGH. The device auto-
matically initiates a new conversion and the cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2411 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50 or 60Hz
plus their harmonics. The filter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2411 incorporates a highly accurate on-
chip oscillator. This eliminates the need for external fre-
quency setting components such as crystals or oscilla-
tors. Clocked by the on-chip oscillator, the LTC2411
achieves a minimum of 110dB rejection at the line fre-
quency (50Hz or 60Hz
±2%).
Ease of Use
The LTC2411 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2411 performs offset and full-scale calibrations in
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with re-
spect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2411 automatically enters an internal reset state
when the power supply voltage VCC drops below approxi-
mately 1.9V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selec-
tion. (See the 2-wire I/O sections in the Serial Interface
Timing Modes section.)
Figure 2. LTC2411 State Transition Diagram
CONVERT
SLEEP
DATA OUTPUT
2411 F02
TRUE
FALSE
CS = LOW
AND
SCK
APPLICATIO S I FOR ATIO
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