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参数资料
| 型号： | LTC2411CMS |
| 英文描述： | Analog-to-Digital Converter， 24-Bit |
| 中文描述： | 模拟到数字转换器，24比特 |
| 文件页数： | 7/40页 |
| 文件大小： | 450K |
| 代理商： | LTC2411CMS |
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LTC2411
15
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 9) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2411 creates its own serial clock by
dividing the internal conversion clock by 8. In the External
SCK mode of operation, the SCK pin is used as input. The
internal or external SCK mode is selected on power-up and
then reselected every time a HIGH-to-LOW transition is
detected at the CS pin. If SCK is HIGH or floating at power-
up or during this transition, the converter enters the inter-
nal SCK mode. If SCK is LOW at power-up or during this
transition, the converter enters the external SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 8), provides the result
of the last conversion as a serial bit stream (MSB first)
during the data output state. In addition, the SDO pin is
used as an end of conversion indicator during the conver-
sion and sleep states.
When CS (Pin 7) is HIGH, the SDO driver is switched to a
high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 7), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2411 will abort any serial data
transfer in progress and start a new conversion cycle
anytime a LOW-to-HIGH transition is detected at the CS
pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with
CS = LOW).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO.
SERIAL INTERFACE TIMING MODES
The LTC2411’s 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
2- or 3-wire I/O, single cycle conversion. The following
sections describe each of these serial interface timing
Table 3. LTC2411 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
FO = LOW
133ms, Output Data Rate
≤ 7.5 Readings/s
(60Hz Rejection)
FO = HIGH
160ms, Output Data Rate
≤ 6.2 Readings/s
(50Hz Rejection)
External Oscillator
FO = External Oscillator
20510/fEOSCs, Output Data Rate ≤ fEOSC/20510 Readings/s
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
SLEEP
As Long As CS = HIGH Until CS = LOW and SCK
DATA OUTPUT
Internal Serial Clock
FO = LOW/HIGH
As Long As CS = LOW But Not Longer Than 1.67ms
(Internal Oscillator)
(32 SCK cycles)
FO = External Oscillator with
As Long As CS = LOW But Not Longer Than 256/fEOSCms
Frequency fEOSC kHz
(32 SCK cycles)
External Serial Clock with
As Long As CS = LOW But Not Longer Than 32/fSCKms
Frequency fSCK kHz
(32 SCK cycles)
APPLICATIO S I FOR ATIO
WU
UU
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