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参数资料
| 型号： | LTC3388IMSE-3#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC 50MA 10MSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 2.8V，3V，3.3V，5V |
| 输入电压： | 2.7 V ~ 20 V |
| 电流 - 输出： | 50mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-MSOP 裸露焊盘 |
LTC3388-1/LTC3388-3
OPERATION
Four selectable voltages are available by tying the output
select bits, D0 and D1, to GND or V IN2 . Table 1 shows the
four D0/D1 codes and their corresponding output voltages
as well as the difference in output voltages between the
LTC3388-1 and LTC3388-3.
Table 1. LTC3388-1/LTC3388-3 Output Voltage Selection
D1 D0 V OUT V OUT Quiescent Current (I VOUT )
0 0 1.2V/2.8V 28nA/66nA
0 1 1.5V/3.0V 36nA/72nA
1 0 1.8V/3.3V 43nA/78nA
1 1 2.5V/5.0V 60nA/120nA
The internal feedback network draws a small amount of
current from V OUT as listed in Table 1.
Dropout Operation
When the input supply voltage decreases towards the
output voltage, the rate of change of inductor current
decreases, reducing the switching frequency of the cur-
rent bursts. Further reduction in input supply voltage will
eventually cause the PMOS to be turned on 100%, i.e.,
DC. The output voltage will then be determined by the
input voltage minus the voltage drop across the PMOS
and the inductor.
Power Good Comparator
A power good comparator causes the PGOOD pin to
go Hi-Z the first time the converter reaches the sleep
threshold of the programmed V OUT , signaling that the
output is in regulation. The PGOOD pin will remain Hi-Z
until V OUT falls to 92% of the desired regulation voltage.
Additionally, if PGOOD is high and V IN falls below the
UVLO falling threshold, PGOOD will remain high until
V OUT falls to 92% of the desired regulation point. This
allows output energy to be used even if the input is lost.
Figure 2 shows the behavior for V OUT = 1.8V and a 10μA
load. At t = 2s V IN becomes high impedance and is dis-
charged by the quiescent current of the LTC3388-1 and
through servicing V OUT . V IN crosses UVLO falling but
PGOOD remains high until V OUT decreases to 92% of the
desired regulation point.
This scenario is likely for cases in which the selected
output voltage is below the UVLO falling threshold. If the
input becomes high impedance and begins to fall it will
be supported by the output through the body diode of
the PMOS switch. For a high enough output voltage the
part will not necessarily enter UVLO while V OUT remains
PGOOD. This is always true for the output voltages avail-
able on the LTC3388-3.
The D0/D1 inputs can be switched while in regulation as
shown in Figure 3. If V OUT is programmed to a voltage with
a PGOOD falling threshold above the old V OUT , PGOOD will
transition low until the new regulation point is reached.
When V OUT is programmed to a lower voltage, PGOOD
will remain high through the transition.
The PGOOD pin is designed to drive a microprocessor or
other chip I/O and is not intended to drive higher current
loads such as an LED.
3.5
C IN = 22μF, C OUT = 100μF, I LOAD = 10μA
6
C OUT = 100μF, I LOAD = 50mA
3.0
5
D1=D0=0
D1=D0=1
D1=D0=0
V IN = UVLO FALLING
2.5
V IN
4
2.0
1.5
V OUT
3
V OUT
2
1.0
0.5
0
PGOOD
1
0
PGOOD = LOGIC 1
0
2
4
6
8
10
0
2
4
6
8
10 12 14 16 18 20
TIME (sec)
338813 F02
Figure 2. PGOOD Operation During Transition to UVLO
TIME (ms)
338813 F03
Figure 3. PGOOD Operation During D0/D1 Transition
338813f
12
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