参数资料
型号: LTC3388IMSE-3#TRPBF
厂商: Linear Technology
文件页数: 14/20页
文件大小: 0K
描述: IC REG BUCK SYNC 50MA 10MSOP
标准包装: 2,500
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 2.8V,3V,3.3V,5V
输入电压: 2.7 V ~ 20 V
电流 - 输出: 50mA
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 10-MSOP 裸露焊盘
LTC3388-1/LTC3388-3
APPLICATIONS INFORMATION
t SLEEP = C OUT HYST
Introduction
The basic LTC3388-1/LTC3388-3 application circuit is
shown on the front page. External components are se-
lected based on the performance requirements of the
application.
Input Capacitor Selection
The input capacitor at V IN should be selected to adequately
bypass the LTC3388-1/LTC3388-3 and filter the switching
current presented by the buck regulator. The V IN capaci-
tor should be rated to withstand the highest voltage ever
present at V IN . It should be placed as close as possible
to the LTC3388-1/LTC3388-3 to force the high frequency
switching current into a tight local loop to minimize EMI.
A 2.2μF ceramic X7R or X5R capacitor should be adequate
for bypassing.
High ripple current, high voltage rating, and low ESR make
ceramic capacitors ideal for switching regulator applica-
tions. However, care must be taken when these capacitors
are used at the input and output. When a ceramic capacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, V IN . A sudden inrush of cur-
rent through the long wires can potentially cause a voltage
spike at V IN large enough to damage the part.
For such applications with inductive source impedance,
such as a long wire, a series RC network may be required
L IN
in parallel with C IN to dampen the ringing of the input
supply. Figure 5 shows this circuit and the typical values
required to dampen the ringing. The RC resistor may be
replaced by a single electrolytic capacitor that has an ESR
equivalent to the needed series resistance of the network.
See Application Note 88 for a complete discussion of this
phenomenon.
Output Capacitor Selection
The duration for which the regulator sleeps depends
on the load current and the size of the output capacitor.
The sleep time decreases as the load current increases
and/or as the output capacitor decreases. The DC sleep
hysteresis window, V HYST , is ±8mV and ±16mV around
the programmed output voltage on the LTC3388-1 and
LTC3388-3 respectively. Ideally this means that the sleep
time is determined by the following equation:
V
I LOAD
This is true for output capacitors on the order of 100μF
or larger, but as the output capacitor decreases towards
10μF delays in the internal sleep comparator along with
the load current may result in the V OUT voltage slewing
past the ±8mV/±16mV thresholds. This will lengthen the
sleep time and increase V OUT ripple. A capacitor less than
10μF is not recommended as V OUT ripple could increase
to an undesirable level.
LTC3388-1/
LTC3388-3
V IN
R
L IN
C IN
4 ? C IN
C IN
338813 F05
Figure 5. Series RC to Reduce V IN Ringing
338813f
14
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