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参数资料
| 型号： | LTC3388IMSE-3#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC 50MA 10MSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 2.8V，3V，3.3V，5V |
| 输入电压： | 2.7 V ~ 20 V |
| 电流 - 输出： | 50mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-MSOP 裸露焊盘 |
LTC3388-1/LTC3388-3
PIN FUNCTIONS
EN (Pin 1): Enable Input. Logic level input referenced to
V IN2 . A logic high on EN will enable the buck converter.
Driving EN to V IN2 will result in no additional quiescent
current on V IN . However, if EN is driven near V IH or V IL
40nA of additional quiescent current can appear on V IN .
STBY (Pin 2): Standby Input. Logic level input referenced
to V IN2 . A logic high on STBY will place the part in standby
mode. Driving STBY to V IN2 will result in no additional
quiescent current on V IN . However, if STBY is driven near
V IH or V IL 40nA of additional quiescent current can ap-
pear on V IN .
CAP (Pin 3): Internal rail referenced to V IN to serve as gate
drive for buck PMOS switch. A 1μF capacitor should be
connected between CAP and V IN . This pin is not intended
for use as an external system rail.
V IN (Pin 4): Input Voltage. A 2.2μF or larger capacitor
should be connected from V IN to GND.
SW (Pin 5): Switch Pin for the Buck Switching Regulator.
A 22μH or larger inductor should be connected from SW
to V OUT .
V OUT (Pin 6): Sense pin used to monitor the output volt-
age and adjust it through internal feedback.
V IN2 (Pin 7): Internal low voltage rail to serve as gate drive
for buck NMOS switch. Also serves as a logic high rail for
output voltage select bits D0 and D1. A 4.7μF capacitor
should be connected from V IN2 to GND. This pin is not
intended for use as an external system rail.
D1 (Pin 8): Output Voltage Select Bit. D1 should be tied
high to V IN2 or low to GND to select desired V OUT (see
Table 1).
D0 (Pin 9): Output Voltage Select Bit. D0 should be tied
high to V IN2 or low to GND to select desired V OUT (see
Table 1).
PGOOD (Pin 10): Power Good Open-Drain NMOS Output.
The PGOOD pin is Hi-Z when V OUT is above 92% of the
target value.
GND (Exposed Pad Pin 11): Ground. The exposed pad
should be connected to a continuous ground plane on the
second layer of the printed circuit board by several vias
directly under the LTC3388-1/LTC3388-3.
338813f
9
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