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参数资料
| 型号： | LTC3388IMSE-3#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 19/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC 50MA 10MSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 2.8V，3V，3.3V，5V |
| 输入电压： | 2.7 V ~ 20 V |
| 电流 - 输出： | 50mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-MSOP 裸露焊盘 |
LTC3388-1/LTC3388-3
PACKAGE DESCRIPTION
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev D)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
(.074
0.102
.004)
0.889
(.035
0.127
.005)
1
1.88
(.074)
1.68
(.066)
0.29
REF
5.23
(.206)
MIN
1.68
(.066
0.102
.004)
3.20 – 3.45
(.126 – .136)
0.05 REF
DETAIL “B”
CORNER TAIL IS PART OF
10
DETAIL “B”
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.305 0.038 0.50
(.0120 .0015) (.0197)
TYP BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 0.102
(.118 .004)
(NOTE 3)
1 0 9 8 7 6
0.497 0.076
(.0196 .003)
REF
0.254
(.010)
DETAIL “A”
0 – 6 TYP
4.90
(.193
0.152
.006)
3.00 0.102
(.118 .004)
(NOTE 4)
GAUGE PLANE
1 2 3 4 5
DETAIL “A”
0.53
(.021
0.152
.006)
1.10
(.043)
MAX
0.86
(.034)
REF
SEATING
0.17 – 0.27
0.50
(.0197)
BSC
0.18
(.007)
PLANE
(.007 – .011)
TYP
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.1016 0.0508
(.004 .002)
MSOP (MSE) 0210 REV D
6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
338813f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
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