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参数资料
| 型号： | LTC3388IMSE-3#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC 50MA 10MSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 2.8V，3V，3.3V，5V |
| 输入电压： | 2.7 V ~ 20 V |
| 电流 - 输出： | 50mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-MSOP 裸露焊盘 |
LTC3388-1/LTC3388-3
APPLICATIONS INFORMATION
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – ( η 1 + η 2 + η 3 + ...)
where η 1, η 2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of
the losses: 1) DC V IN operating current while active and
in sleep, 2) MOSFET gate charge loss, and 3) I 2 R losses.
The V IN operating current dominates the efficiency loss
at very low load currents whereas the gate charge and
I 2 R loss dominates the efficiency loss at medium to high
load currents.
1. The DC V IN current is the average of the quiescent
supply currents, given in the electrical characteristics,
in the active and sleep modes. This can be estimated
with the following equation:
2. Internal MOSFET gate charge currents result from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched
from high to low to high again, a packet of charge, dQ,
moves from V IN to ground. The resulting dQ/dt is the
current out of V IN that is typically larger than the DC bias
current. Of course, this switching current only appears
when the buck is on and is important at high load cur-
rents. Gate charge loss can be reduced by increasing
the inductor, thereby reducing the switching frequency
when the buck is active.
3. I 2 R losses are calculated from the resistances of the
internal switches, R SW , and the external inductor DCR.
When switching, the average output current flowing
through the inductor is “chopped” between the high
side PMOS switch and the low side NMOS switch. Thus,
the series resistance looking back into the switch pin is
a function of the top and bottom switch on-resistance
and the duty cycle (DC = V OUT /V IN ) as follows:
R SW = (R P,BUCK )DC + (R N,BUCK )(1 – DC)
The on-resistance for both the top and bottom MOSFETs
can be obtained from the curves in the Typical Perfor-
I Q(ACTIVE) + ? 1 ?
I LOAD ?
I BUCK ? ? Q(SLEEP)
I VIN(AVG) =
I LOAD
I BUCK
?
?
I
mance Characteristics section. Thus, to obtain the I 2 R
losses, simply add R SW to the DCR and multiply the
result by the square of the average output current:
where I BUCK is the average current being delivered
from the buck converter, typically I PEAK /2. For very
light loads I Q(SLEEP) will dominate this loss term which
is why the extremely low quiescent current in sleep of
the LTC3388-1/LTC3388-3 is critical.
I 2 R Loss = I O2 (R SW + DCR)
This loss term only occurs when the buck is operating
and must be multiplied by the percentage of time the
buck is operating versus sleeping or I LOAD /I BUCK to see
its overall effect.
Other losses, including C IN and C OUT ESR dissipative losses
and inductor core losses, generally account for less than
2% of the total power loss.
338813f
16
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