- 您现在的位置：买卖IC网 > PDF目录14798 > LTC3615EUF#PBF (Linear Technology)IC REG BUCK SYNC ADJ 3A DL 24QFN PDF资料下载
参数资料
| 型号： | LTC3615EUF#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 24/32页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A DL 24QFN |
| 标准包装： | 91 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.6 V ~ 5.5 V |
| 输入电压： | 2.25 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 400kHz ~ 4MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 24-QFN 裸露焊盘（4x4） |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页第29页第30页第31页第32页
LTC3615/LTC3615-1
APPLICATIONS INFORMATION
DDR Application
The LTC3615 can be used in DDR memory power supply
applications by tying the SRLIM pin to SV IN . In DDR mode,
the maximum slew rate is selected. The output can both
source and sink current. Current sinking is typically limited
to 1.5A, for 1MHz frequency and 1μH inductance, but can
be lower at higher frequencies and low output voltages.
If higher ripple current can be tolerated, smaller inductor
values can increase the sink current limit. See the Typical
Performance Characteristics curves for more information.
In addition, in DDR mode, lower external reference volt-
ages and tracking output voltages between channels are
possible. See the Output Voltage Tracking Input section.
Single, Low Ripple 6A Output Application
The LT3615 can generate a single, low ripple 6A output if
the outputs of the two switching regulators are tied together
and share a single output capacitor (see Figure 15 on back
of data sheet). In order to evenly share the current between
the two regulators, it is needed to connect pins FB1 to
FB2, ITH1 to ITH2 and to select forced continuous mode
at the MODE pin. To achieve lowest ripple, 90°, or better,
180°, antiphase is selected by connecting the PHASE pin
to midrail or SV IN . There are several advantages to this
2-phase buck regulator. Ripple currents at the input and
output are reduced, reducing voltage ripple and allowing
the use of smaller, less expensive capacitors. Although
two inductors are required, each will be smaller than the
inductor required for a single-phase regulator. This may
be important when there are tight height restrictions on
the circuit.
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V IN quiescent current and I 2 R losses. The V IN
quiescent current loss dominates the efficiency loss at
very low load currents whereas the I 2 R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
of little consequence.
1. The V IN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from V IN to ground. The resulting dQ/dt is the current
out of V IN due to gate charge, and it is typically larger
than the DC bias current. Both the DC bias and gate
charge losses are proportional to V IN , thus, their effects
will be more pronounced at higher supply voltages.
2. I 2 R losses are calculated from the resistances of the
internal switches, R SW , and external inductor R L . In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R DS(ON) and the duty cycle
(DC), as follows:
R SW = (R DS(ON)TOP )(DC) + (R DS(ON)BOT )(1 – DC)
The R DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. To obtain I 2 R losses, simply add R SW to R L and
multiply the result by the square of the average output
current.
Other losses, including C IN and C OUT ESR dissipative losses
and inductor core losses, generally account for less than
2% of the total loss.
Thermal Considerations
In most applications, the LTC3615 does not dissipate
much heat due to its high efficiency. However, in ap-
plications where the LTC3615 is running at high ambient
24
For more information www.linear.com/LTC3615
3615fb
相关PDF资料 |
PDF描述 |
|---|---|
| RBC25DCAD | CONN EDGECARD 50POS R/A .100 SLD |
| RBB05DHFR | CONN EDGECARD 10POS .050 SMD |
| LTC3615EUF-1#PBF | IC REG BUCK SYNC ADJ 3A DL 24QFN |
| MAX6423US24+T | IC MPU/RESET CIRC 2.40V SOT143-4 |
| LT1076CR#PBF | IC REG MULTI CONFIG ADJ 2A D2PAK |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC3615HFE#PBF | 制造商:Linear Technology 功能描述:IC REG BUCK SYNC ADJ 3A 24TSSOP |
| LTC3615HFE#TRPBF | 制造商:Linear Technology 功能描述:IC REG BUCK SYNC ADJ 3A 24TSSOP |
| LTC3615HFE-1#PBF | 制造商:Linear Technology 功能描述:IC REG BUCK SYNC ADJ 3A 24TSSOP |
| LTC3615HFE-1#TRPBF | 制造商:Linear Technology 功能描述:IC REG BUCK SYNC ADJ 3A 24TSSOP |
| LTC3615HUF#PBF | 制造商:Linear Technology 功能描述:IC REG BUCK SYNC ADJ 3A 24TSSOP |
发布紧急采购，3分钟左右您将得到回复。