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| 型号： | LTC3859EUHF#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 31/42页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM CM 38-QFN |
| 标准包装： | 52 |
| PWM 型： | 电流模式，Burst Mode? |
| 输出数： | 3 |
| 频率 - 最大： | 850kHz |
| 占空比： | 100% |
| 电源电压： | 4.5 V ~ 38 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 包装： | 管件 |
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LTC3859
APPLICATIONS INFORMATION
V OUT ? ?
Δ I L =
? 1 ? V
(f)(L) ?
IN(NOMINAL) ?
t ON(MIN) =
=
= 429ns
amount equal to DI LOAD(ESR) , where ESR is the effective
series resistance of C OUT . D I LOAD also begins to charge or
discharge C OUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return V OUT to its steady-state value. During this recovery
time V OUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the I TH pin not only allows
optimization of control loop behavior, but it also provides
a DC coupled and AC ?ltered closed loop response test
point. The DC step, rise time and settling at this test
point truly re?ects the closed loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I TH
external components shown in Figure 16 will provide an
adequate starting point for most applications.
The I TH series RC-CC ?lter sets the dominant pole-zero
loop compensation. The values can be modi?ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the ?nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and I TH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Placing a power MOSFET directly across the output
capacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better to
look at the I TH pin signal which is in the feedback loop and
is the ?ltered and compensated control loop response.
The gain of the loop will be increased by increasing
RC and the bandwidth of the loop will be increased by
decreasing CC. If RC is increased by the same factor
that CC is decreased, the zero frequency will be kept the
same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C OUT , causing a rapid drop in V OUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C LOAD to C OUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 ? C LOAD . Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
Buck Design Example
As a design example for one of the buck channels channel,
assume V IN = 12V (NOMINAL) , V IN = 22V (MAX) , V OUT = 3.3V,
I MAX = 6A, V SENSE(MAX) = 50mV, and f = 350kHz.
The inductance value is chosen ?rst based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the FREQ pin
to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
V OUT
?
A 3.9μH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 6.88A. Increasing the ripple
current will also help ensure that the minimum on-time
of 95ns is not violated. The minimum on-time occurs at
maximum V IN :
V OUT 3.3V
V IN(MAX) (f) 22V(350kHz)
3859fa
31
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