参数资料
| 型号： | LTC4101EG#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 20/30页 |
| 文件大小： | 0K |
| 描述： | IC CNTRLR BATT CHRG 24-SSOP |
| 标准包装： | 59 |
| 功能： | 充电管理 |
| 电池化学： | 智能电池 |
| 电源电压： | 6 V ~ 28 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 管件 |
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LTC4101
OPERATION
The Voltage DAC Block
I PROG
(FROM CA1 AMP)
Note that the charger output voltage is offset by V REF .
Therefore, the value of V REF is subtracted from the SMBus
ChargingVoltage() value in order for the output voltage to
I DC
20
R SET
V REF
I TH
19
be programmed properly (without offset). If the Charging-
Voltage() value is below the nominal reference voltage of
the charger, nominally 1.104V, the charger output voltage
Δ - ∑
MODULATOR
CHARGING_CURRENT
VALUE
is programmed to zero. In addition, if the ChargingVolt-
age() value is above the limit set by the V LIM pin, then the
charger output voltage is set to the value determined by
Figure 7. Current DAC Operation
4101 F07
the V LIM resistor and the VOLTAGE_OR bit is set. These
limits are demonstrated in Figure 6.
When a value less than 1/16th of the maximum current
allowed by I LIM is applied to the current DAC input, the
current DAC enters a different mode of operation called
6
5
4
3
2
1
R VLIM = 33k
LOWI. The current DAC output is pulse width modulated
with a high frequency clock having a duty cycle value of
1/8. Therefore, the maximum output current provided by
the charger is I MAX /8. The delta-sigma output gates this
low duty cycle signal on and off. The delta-sigma shift
registers are then clocked at a slower rate, about 45ms/bit,
so that the charger has time to settle to the I MAX /8 value.
The resulting average charging current is equal to that
requested by the ChargingCurrent() value.
0
0
1
2 3 4 5
PROGRAMMED VALUE (V)
6
4101 F06
Note: The LOWI mode can be disabled by setting the
NO_LOWI bit in the LTC0() function.
When wake-up is asserted to the current DAC block, the
NOTE: THE LTC4101 CAN BE PROGRAMMED WITH ChargingVoltage() FUNCTION VALUES
BETWEEN 1.104V AND 2.9V, HOWEVER, THE BATTERY CHARGER CONTROLLER OUTPUT
VOLTAGE MAY BE ZERO WITH PROGRAMMED VALUES BELOW 2.9V.
Figure 6. Transfer Function of Charger
The Current DAC Block
The current DAC is a delta-sigma modulator which controls
the effective value of an external resistor, R SET , used to
set the current limit of the charger. Figure 7 is a simpli?ed
diagram of the DAC operation. The delta-sigma modulator
and switch convert the ChargingCurrent() value, received
via the SMBus, to a variable resistance equal to:
1.25R SET /[ChargingCurrent()/I LIM[x] ] = R IDC
Therefore, programmed current is equal to:
I CHARGE = (102.3mV/R SENSE ) (ChargingCurrent()/I LIM[x] ),
for ChargingCurrent() < I LIM[x] .
delta-sigma is then ?xed at a value equal to 80mA, inde-
pendent of the I LIM setting.
Input FET
The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLP pin,
and provides an indication of this condition at both the
CHGEN pin and the PWR_FAIL bit in the ChargerStatus()
register. It also controls the gate of the input FET to keep
a low forward voltage drop when charging and prevents
reverse current ?ow through the input FET.
If the input voltage is less than V CLP , it must go at least
130mV higher than V CLP to activate the charger. The CHGEN
pin is forced low unless this condition is met. The gate
of the input FET is driven to a voltage suf?cient to keep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLP drops to less than 25mV,
the input FET is turned off slowly. If the voltage between
4101fa
20
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