参数资料
型号: M25P10-AVMB6T/X
厂商: NUMONYX
元件分类: PROM
英文描述: FLASH 2.7V PROM, DSO8
封装: 2 X 3 MM, ROHS COMPLIANT, UFDFPN-8
文件页数: 16/51页
文件大小: 1103K
代理商: M25P10-AVMB6T/X
M25P10-A
Instructions
23/51
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
Figure 11.
Write Status Register (WRSR) instruction sequence
Table 7.
Protection modes
W
signal
SRWD
bit
Mode
Write protection of the
Status Register
Memory content
Protected area(1)
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
Unprotected
area(1)
10
Software
protected
(SPM)
Status Register is writable (if
the WREN instruction has set
the WEL bit)
The values in the SRWD, BP1
and BP0 bits can be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program
and Sector Erase
instructions
00
11
01
Hardware
protected
(HPM)
Status Register is hardware
write protected
The values in the SRWD, BP1
and BP0 bits cannot be
changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program
and Sector Erase
instructions
C
D
AI02282D
S
Q
2
1
3456789 10 11 12 13 14 15
High Impedance
Instruction
Status
Register In
0
765432
0
1
MSB
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