参数资料
型号: M28F220
厂商: 意法半导体
英文描述: 2Mbit (256Kb x8 or 128Kb x16, Boot Block) Flash Memory(2Mb闪速存储器)
中文描述: 2Mbit的(256Kb的x8或128KB的x16插槽,引导块)快闪记忆体(处理器闪速存储器)
文件页数: 8/32页
文件大小: 226K
代理商: M28F220
Mnemon
ic
Bit
Name
Logic
Level
Definition
Note
P/ECS
7
P/E.C. Status
’1’
Ready
Indicates the P/E.C. status, check during Program
or Erase, and on completion before checking bits
b4 or b5 for Program or Erase Success
’0’
Busy
ESS
6
Erase
Suspend
Status
’1’
Suspended
On an EraseSuspend instruction P/ECS and
ESS bits are set to ’1’. ESS bit remains ’1’until an
Erase Resume instructionis given.
’0’
In progress or
Completed
ES
5
Erase Status
’1’
Erase Error
ES bit is set to ’1’ if P/E.C. has applied the
maximum number of erase pulses to the block
without achieving an erase verify.
’0’
Erase Success
PS
4
Program
Status
’1’
Program Error
PS bit set to ’1’ if the P/E.C.has failed to program
a byte or word.
’0’
Program
Success
VPPS
3
V
PP
Status
’1’
V
PP
Low, Abort
VPPS bit is set if the V
PP
voltage is below
V
(min) when a Program or Erase instruction
has been executed.
’0’
V
PP
OK
2
Reserved
1
Reserved
0
Reserved
Notes:
Logic level ’1’is High,’0’ is Low.
Table8. StatusRegister
Program (PG) Instruction.
This instruction uses
two write operations.The first command written is
the Program Set-up command 40h (or 10h). A
secondwriteoperationlatchestheAddressandthe
Data to be written and starts the P/E.C. Read
operationsoutput the statusregister after the pro-
gramminghas started.
Memoryprogrammingis onlymade bywriting’0’in
place of ’1’ in a byte or word.
During the execution of the programming by the
P/E.C., the memory accepts only the RSR (Read
StatusRegister)instruction.TheStatusRegisterbit
b7 returns’0’while theprogrammingis in progress
and’1’whenithascompleted.Aftercompletionthe
Statusregisterbitb4 returns’1’ if there has beena
Program Failure. Status Register bit b3 returns a
’1’ if V
PP
does not remain at V
PPH
when program-
ming is attemptedand/or duringprogramming.
V
PP
mustbeat V
PPH
whenprogramming,program-
ming should not be attempted when V
PP
< V
PPH
as the results will be uncertain. Programming
abortsif V
PP
dropsbelowV
PPH
or RP goes Low. If
aborted the data may be incorrect. Then after
having cleared the Status Register (CLRS), the
memory must be erasedand re-programmed.
Clear Status Register (CLRS) Instruction.
The
ClearStatusRegisterusesa singlewriteoperation
which clears bits b3, b4 and b5, if latched to ’1’ by
the P/E.C., to ’0’. Its use is necessary before any
new operationwhen an error has been detected.
8/32
M28F220
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