- 您现在的位置：买卖IC网 > PDF目录299435 > M50FLW080AN5G (STMICROELECTRONICS) 1M X 8 FLASH 3V PROM, 11 ns, PDSO40 PDF资料下载
参数资料
| 型号： | M50FLW080AN5G |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 1M X 8 FLASH 3V PROM, 11 ns, PDSO40 |
| 封装： | 10 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-40 |
| 文件页数： | 16/64页 |
| 文件大小： | 534K |
| 代理商： | M50FLW080AN5G |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页
M50FLW080A, M50FLW080B
Bus operations
Figure 9.
LPC Bus Write waveforms (1 byte)
Table 9.
LPC Bus Write field definitions (1 byte)
Clock
Cycle
Number
Clock
Cycle
Count
Field
LAD0-
LAD3
Memory
I/O
Description
1
START
0000b
I
On the rising edge of CLK with LFRAME Low,
the contents of LAD0-LAD3 must be 0000b to
indicate the start of a LPC cycle.
21
CYCTYPE
+ DIR
011Xb
I
Indicates the type of cycle. Bits 3:2 must be
01b. Bit 1 indicates the direction of transfer: 1b
for write. Bit 0 is don’t care (X).
3-10
8
ADDR
XXXX
I
A 32-bit address is transferred, with the most
significant nibble first. A23-A31 must be set to
1. A22=1 for memory access, and A22=0 for
register access. Table 5 shows the appropriate
values for A21-A20.
11-12
2
DATA
XXXX
I
Data transfer is two cycles, starting with the
least significant nibble.
13
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
14
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-
LAD3 during this cycle.
15
1
SYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3 to
0000b, indicating it has received data or a
command.
16
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to
1111b, indicating a turnaround cycle.
17
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs and
the host takes control of LAD0-LAD3.
AI04430
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START
CYCTYPE
+ DIR
ADDR
DATA
TAR
SYNC
TAR
1182212
相关PDF资料 |
PDF描述 |
|---|---|
| M50FLW080BN5G | 1M X 8 FLASH 3V PROM, 11 ns, PDSO40 |
| M5218 | CAP .68UF 50V ELECT MVK BI SMD |
| M5278L12 | 12 V FIXED POSITIVE REGULATOR, PBCY3 |
| M54193P | TELEPHONE RINGER CKT, PDIP8 |
| M54HC4066F1 | QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, CDIP14 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M50FLW080AN5P | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080AN5T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080AN5TG | 功能描述:IC FLASH 8MBIT 33MHZ 40TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:移动 SDRAM 存储容量:256M（8Mx32） 速度:133MHz 接口:并联 电源电压:1.7 V ~ 1.95 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:带卷 (TR) 其它名称:557-1327-2 |
| M50FLW080AN5TP | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080ANB5 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
发布紧急采购，3分钟左右您将得到回复。