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参数资料
| 型号： | M50FLW080AN5G |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 1M X 8 FLASH 3V PROM, 11 ns, PDSO40 |
| 封装： | 10 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-40 |
| 文件页数： | 6/64页 |
| 文件大小： | 534K |
| 代理商： | M50FLW080AN5G |
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Signal descriptions
M50FLW080A, M50FLW080B
2.1.4
General-purpose inputs (GPI0-GPI4)
The General Purpose Inputs can be used as digital inputs for the CPU to read, with their
contents being available in the General Purpose Inputs Register. The pins must have stable
data throughout the entire cycle that reads the General Purpose Input Register. These pins
should be driven Low, VIL, or High, VIH, and must not be left floating.
2.1.5
Interface configuration (IC)
The Interface Configuration input selects whether the FWH/LPC interface or the
Address/Address Multiplexed (A/A Mux) Interface is used. The state of the Interface
Configuration, IC, should not be changed during operation of the memory device, except for
selecting the desired interface in the period before power-up or during a Reset.
To select the FWH/LPC Interface, the Interface Configuration pin should be left to float or
driven Low, VIL. To select the Address/Address Multiplexed (A/A Mux) Interface, the pin
should be driven High, VIH. An internal pull-down resistor is included with a value of RIL;
there will be a leakage current of ILI2 through each pin when pulled to VIH.
2.1.6
Interface Reset (RP)
The Interface Reset (RP) input is used to reset the device. When Interface Reset (RP) is
driven Low, VIL, the memory is in Reset mode (the outputs go to high impedance, and the
current consumption is minimized). When RP is driven High, VIH, the device is in normal
operation. After exiting Reset mode, the memory enters Read mode.
2.1.7
CPU Reset (INIT)
The CPU Reset, INIT, signal is used to Reset the device when the CPU is reset. It behaves
identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
2.1.8
Clock (CLK)
The Clock, CLK, input is used to clock the signals in and out of the Input/Output
Communication Pins, FWH0/LAD0-FWH3/LAD3. The Clock conforms to the PCI
specification.
2.1.9
Top Block Lock (TBL)
The Top Block Lock input is used to prevent the Top Block (Block 15) from being changed.
When Top Block Lock, TBL, is driven Low, VIL, program and erase operations in the Top
Block have no effect, regardless of the state of the Lock Register. When Top Block Lock,
TBL, is driven High, VIH, the protection of the Block is determined by the Lock Registers.
The state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks
0 to 14). For details, see Appendix A.
Top Block Lock, TBL, must be set prior to a program or erase operation being initiated, and
must not be changed until the operation has completed, otherwise unpredictable results
may occur. Similarly, unpredictable behavior is possible if WP is changed during Program or
Erase Suspend, and care should be taken to avoid this.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M50FLW080AN5P | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080AN5T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080AN5TG | 功能描述:IC FLASH 8MBIT 33MHZ 40TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:移动 SDRAM 存储容量:256M（8Mx32） 速度:133MHz 接口:并联 电源电压:1.7 V ~ 1.95 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:带卷 (TR) 其它名称:557-1327-2 |
| M50FLW080AN5TP | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080ANB5 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
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