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参数资料
| 型号： | M50FLW080AN5G |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 1M X 8 FLASH 3V PROM, 11 ns, PDSO40 |
| 封装： | 10 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-40 |
| 文件页数： | 5/64页 |
| 文件大小： | 534K |
| 代理商： | M50FLW080AN5G |
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M50FLW080A, M50FLW080B
Signal descriptions
2
Signal descriptions
There are two distinct bus interfaces available on this device. The active interface is selected
before power-up, or during Reset, using the Interface Configuration Pin, IC.
The signals for each interface are discussed in the Firmware Hub/low-pin-count (FWH/LPC)
signal descriptions section and the Address/Address multiplexed (A/A Mux) signal
descriptions section, respectively, while the supply signals are discussed in the Supply
signal descriptions section.
2.1
Firmware Hub/low-pin-count (FWH/LPC) signal descriptions
2.1.1
Input/Output communications (FWH0/LAD0-FWH3/LAD3)
All Input and Output Communications with the memory take place on these pins. Addresses
and Data for Bus Read and Bus Write operations are encoded on these pins.
2.1.2
Input communication frame (FWH4/LFRAME)
The Input Communication Frame (FWH4/LFRAME) signal indicates the start of a bus
operation. When Input Communication Frame is Low, VIL, on the rising edge of the Clock, a
new bus operation is initiated. If Input Communication Frame is Low, VIL, during a bus
operation then the operation is aborted. When Input Communication Frame is High, VIH, the
current bus operation is either proceeding or the bus is idle.
2.1.3
Identification inputs (ID0-ID3)
Up to 16 memories can be addressed on a bus, in the Firmware Hub (FWH) mode. The
Identification Inputs allow each device to be given a unique 4-bit address. A ‘0’ is signified
on a pin by driving it Low, VIL, or leaving it floating (since there is an internal pull-down
resistor, with a value of RIL). A ‘1’ is signified on a pin by driving it High, VIH (and there will
be a leakage current of ILI2 through the pin).
By convention, the boot memory must have address ‘0000’, and all additional memories are
given addresses, allocated sequentially, from ‘0001’.
In the Low Pin Count (LPC) mode, the identification Inputs (ID2-ID3) can address up to 4
memories on a bus. In the LPC mode, the ID0 and ID1 signals are Reserved for Future Use
(RFU). The value on address A20-A21 is compared to the hardware strapping on the ID2-
ID3 lines to select the memory that is being addressed. For an address bit to be ‘1’, the
corresponding ID pin can be left floating or driven Low, VIL (again, with the internal pull-
down resistor, with a value of RIL). For an address bit to be ‘0’, the corresponding ID pin
must be driven High, VIH (and there will be a leakage current of ILI2 through the pin, as
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M50FLW080AN5P | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080AN5T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080AN5TG | 功能描述:IC FLASH 8MBIT 33MHZ 40TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:移动 SDRAM 存储容量:256M（8Mx32） 速度:133MHz 接口:并联 电源电压:1.7 V ~ 1.95 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:带卷 (TR) 其它名称:557-1327-2 |
| M50FLW080AN5TP | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080ANB5 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
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