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参数资料
| 型号： | M50FLW080AN5G |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 1M X 8 FLASH 3V PROM, 11 ns, PDSO40 |
| 封装： | 10 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-40 |
| 文件页数： | 7/64页 |
| 文件大小： | 534K |
| 代理商： | M50FLW080AN5G |
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M50FLW080A, M50FLW080B
Signal descriptions
2.1.10
Write Protect (WP)
The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 14) from being
changed. When Write Protect, WP, is driven Low, VIL, Program and Erase operations in the
Main Blocks have no effect, regardless of the state of the Lock Register. When Write
Protect, WP, is driven High, VIH, the protection of the Block or Sector is determined by the
Lock Registers. The state of Write Protect, WP, does not affect the protection of the Top
Block (Block 15). For details, see Appendix A.
Write Protect, WP, must be set prior to a Program or Erase operation is initiated, and must
not be changed until the operation has completed otherwise unpredictable results may
occur. Similarly, unpredictable behavior is possible if WP is changed during Program or
Erase Suspend, and care should be taken to avoid this.
2.1.11
Reserved for Future Use (RFU)
Reserved for Future Use (RFU). These pins do not presently have assigned functions. They
must be left disconnected, except for ID0 and ID1 (when in LPC mode) which can be left
connected. The electrical characteristics for these signals are as described in the
“Identification inputs (ID0-ID3)” section.
2.2
Address/Address multiplexed (A/A Mux) signal descriptions
2.2.1
Address inputs (A0-A10)
The Address Inputs are used to set the Row Address bits (A0-A10) and the Column
Address bits (A11-A19). They are latched during any bus operation by the Row/Column
Address Select input, RC.
2.2.2
Data inputs/outputs (DQ0-DQ7)
The Data Inputs/Outputs hold the data that is to be written to or read from the memory. They
output the data stored at the selected address during a Bus Read operation. During Bus
Write operations they carry the commands that are sent to the Command Interface of the
internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write
operation.
2.2.3
Output Enable (G)
The Output Enable signal, G, controls the output buffers during a Bus Read operation.
2.2.4
Write Enable (W)
The Write Enable signal, W, controls the Bus Write operation of the Command Interface.
2.2.5
Row/Column Address Select (RC)
The Row/Column Address Select input selects whether the Address Inputs are to be latched
into the Row Address bits (A0-A10) or the Column Address bits (A11-A19). The Row
Address bits are latched on the falling edge of RC whereas the Column Address bits are
latched on its rising edge.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M50FLW080AN5P | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080AN5T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080AN5TG | 功能描述:IC FLASH 8MBIT 33MHZ 40TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:移动 SDRAM 存储容量:256M（8Mx32） 速度:133MHz 接口:并联 电源电压:1.7 V ~ 1.95 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:带卷 (TR) 其它名称:557-1327-2 |
| M50FLW080AN5TP | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080ANB5 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
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