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| 型号： | MA31750 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | High Performance MIL-STD-1750 Microprocessor |
| 中文描述： | 高性能的MIL - STD - 1750微处理器 |
| 文件页数： | 10/42页 |
| 文件大小： | 436K |
| 代理商： | MA31750 |
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MA31750
10/42
Figure 13: XIO Command Channel Grouping
XIO command addresses are grouped by the Standard
according to function. Certain groups are ‘reserved’ and must
not be implemented. Attempts to read or write these areas will
be prevented by the processor and a fault will be logged in the
fault register. Other groups are designated ‘spare’ and may be
implemented as required by the system designer. Note,
however, that there is a third group which access system
resources such as MMU page registers and interrupt control
registers which are not available to the user to implement. A
summary of the XIO map is provided in figure 13, whilst the
detailed list of implemented command addresses is shown in
Figure 20c.
The VIO (Vectored IO) command allows a number of IO
operations to be executed in a sequence from a table.
Applications Note 8 gives further information on the use of this
command.
Both XIO and VIO are priveleged commands and as such
can only be executed when the Status Word PS field is zero.
4.3. PROCESSOR STATE AND PRIVILEGED
INSTRUCTIONS
The Processor State is defined by a 4-bit value held in the
processor Status Word. If the value is made non-zero then
attempts to execute the commands XIO, VIO or LST will be
aborted and a fault will be raised. This is intended to deny
direct access to the hardware from user applications (running
in PS
≠
0), whilst allowing the Operating System (operating with
PS=0) access to the system IO and interrupt resources.
If an MMU is present on the system the PS field is used in
conjunction with the page register Access Key field to provide
a further level of protection to the system. When PS=0 access
is granted to all pages, irrespective of their key value. If PS is
non-zero, access is only permitted if the Access Key is equal to
the PS value, or the Access Key is 15. Access Key 15 should
be applied to a shared area of code or data, and is accessable
to all PS values.
Output
0000-03FF 8000-83FF
0400-1FFF 8400-9FFF
2000-20FF A000-A0FF CPU and auxiliary register control
2100-2FFF A100-AFFF Reserved
3000-3FFF B000-BFFF Spare
4000-40FF C000-CFFF CPU and auxiliary register control
4100-4CFF C100-CCFF Reserved
4D00-4FFF CD00-CFFF Extended memory protect RAM
5000-50FF D000-D0FF Memory protect RAM
5100-51FF D100-D1FF MMU Instruction Page Registers
5200-52FF D200-D2FF MMU Operand Page Registers
5300-7FFF D300-FFFF Spare
Input
Usage
PIO
Spare
4.4. USING START-UP ROM
The transition between code execution from Start-up ROM
and system RAM must be made with care. If a system overlays
RAM with the Start-Up ROM and the transition is made by
simply executing XIO DSUR from the ROM, then the
instruction pipeline will contain the value stored in the ROM
location immediately following the XIO DSUR command. This
value will be treated as an instruction and the processor will
attempt to execute it. In such cases, it is recommended that
DSUR be followed by an unconditional branch instruction with
offset, i.e. the BR instruction. An alternative approach is simply
to jump to a portion of RAM not overlaid by the Start-Up ROM
and execute DSUR from RAM.
4.5. USING SOFTWARE TIMERS A AND B
The MA31750 implements the two software timers, A and
B as defined in the MIL-STD 1750A specification. These are
general purpose timers which are clocked at 100kHz and
10kHz respectively, giving clock ‘tick’ intervals of 10us and
100us respectively. They may be started using the XIO TAS
and XIO TBS instructions, and stopped using XIO TAH and
XIO TBH. If a timer is allowed to overflow (FFFF
16
- 0000
16
) it
will generate pending interrupt levels 7 (A) or 9 (B).
In 1750B mode each timer has associated with it a reset
register which may be loaded with any 16-bit value from
software. If a timer is allowed to overflow, an automatic reset
will take place which will reload the timer with the value held in
its on-chip reset register, provided that the timer had
previously been loaded using XIO OTA/OTB. If this is not the
case, then the timers will reset to zero on overflow. Each of the
reset registers is initialised to zero but may be changed using
XIO OTAR or XIO OTBR.
4.6. FAULT MASK REGISTER
A fault mask register is accessible in 1750B mode. Its
function is similar to that of the Interrupt Mask register and
allows selective enabling and disabling of all bits in the Fault
Register. All faults are maskable. Setting a bit in this register
allows the corresponding fault bit to be seen by the system.
The mask register is loaded with FFFF
16
on initialisation.
4.7. GENERAL REGISTERS R0-R15
There are 16 general purpose registers defined by MIL-
STD-1750; each is 16-bits wide. Adjacent registers may be
concatenated to provide storage for the larger data formats
(Double Integer and Float - 32-bit; Extended Float - 48-bit).
The first register in the set stores the most significant data
word and is the register specified when referring to the value.
Wrap-around occurs between R15 and R0.
Although generally all registers are the same, certain
registers are notionally assigned to particular tasks, see figure
15.
相关PDF资料 |
PDF描述 |
|---|---|
| MA31751 | Memory Management & Block Protection Unit |
| MA31753 | DMA Controller (DMAC) For An MA31750 System |
| MA31755 | 16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| MA3690 | 1553B Bus Controller/Remote Terminal |
| MA3691 | 1553B Bus Controller/Remote Terminal |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MA31751 | 制造商:DYNEX 制造商全称:Dynex Semiconductor 功能描述:Memory Management & Block Protection Unit |
| MA31753 | 制造商:DYNEX 制造商全称:Dynex Semiconductor 功能描述:DMA Controller (DMAC) For An MA31750 System |
| MA31755 | 制造商:DYNEX 制造商全称:Dynex Semiconductor 功能描述:16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| MA318 | 功能描述:CPU与芯片冷却器 INTEL P111 FC-PGA RoHS:否 制造商:ADLINK Technology 尺寸: 电压额定值: 功率额定值: 速度: 气流: 系列: |
| MA3180 | 制造商:PANASONIC 制造商全称:Panasonic Semiconductor 功能描述:Silicon planar type |
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