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参数资料
| 型号： | MA31750 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | High Performance MIL-STD-1750 Microprocessor |
| 中文描述： | 高性能的MIL - STD - 1750微处理器 |
| 文件页数： | 34/42页 |
| 文件大小： | 436K |
| 代理商： | MA31750 |
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MA31750
34/42
Pin Name
Function
Description
POWER
VDD
GND
Power Supply
Ground
DC power supply input - nominally +5V.
0V reference point.
CLOCK SIGNALS
CLK
System Clock
Schmitt Input clock signal.
For correct operation of the timers the CLK frequency should be at least 9 times that of
TCLK.
Buffered reference clock derived directly from the internal clock. This signal is used to
reference all of the external strobes and internal timing events and may be used to
synchronise an external system to the processor.
This Schmitt input clock is used by the internal 16-bit timers A and B and by the Trigger-Go-
counter. MlL-STD-1750 requires this signal to have a frequency of 100kHz.
CLKOUT
Clock Out
TCLK
Timer Clock
100kHz sq. wave
SYSTEM BUSES
A00-A15
Address bus
A00 is MSB
Data bus
D00 is MSB
An active-high address bus which is input during bus cycles not assigned to this CPU. A00
is the most significant bit.
An active-high data bus which is tristate during bus cycles not assigned to this CPU. D00 is
the most significant bit. D16 is the optional parity check bit.
D00-D16
BUS CONTROL
AS
Address Strobe
Active HIGH
This active-high bidirectional signal establishes the beginning and end of each bus cycle.
The trailing edge (high to low transition) is used to sample bus cycle-related faults into the
fault register. The leading edge guarantees that a valid address is on the address bus.
During cycles not assigned to this CPU the AS line is an input to allow the falling edge to
continue to latch bus cycle related faults into the fault register.
This active-low signal indicates the presence of data on the system data bus. During a read
cycle DSN goes low to indicate that the processor is requesting data from the bus, whilst in
a write cycle DSN indicates that data is present on the bus. This signal is tristate in bus
cycles not assigned to this CPU.
This signal indicates whether the current bus cycle is accessing memory (high) or IO (low)
addressing space. This signal becomes valid shortly after the start of a machine cycle and
remains valid throughout. M/ION becomes an input on cycles not assigned to the CPU to
ensure that faults are latched into the correct bit of the fault register.
This signal indicates the direction of data transfer on the system data bus. Data is read in
by the processor when high, and written out when low. This signal becomes valid shortly
after the start of a machine cycle and remains valid throughout. RD/WN is tristate during
cycles not assigned to this CPU.
This signal indicates whether the current bus cycle is accessing operand (high) or
instruction (low) addressing space. This signal becomes valid shortly after the start of a
machine cycle and remains valid throughout. O/IN is an input during cycles not assigned to
this CPU, to ensure correct operation of the MFPR and the MFAR.
This active-low output is asserted low with DSN during read cycles. It is driven high on the
same clock edge as that used by the processor to latch the input data. This signal is
tristate in bus cycles not assigned to this CPU.
This active-low output signal is asserted low with DSN during write cycles. The rising edge
should be used by the system to latch data from the data bus. This signal is tristate in bus
cycles not assigned to this CPU.
This input signal allows the basic machine cycle of the processor to be extended to
accommodate slower peripheral or memory devices. Ready may be asserted high to add an
integer number of CLK cycles (wait states) to the machine cycle. The line must be asserted
low to allow processing to proceed. RDYN has no effect on cycles dedicated to internal
operations.
Note:
If RDYN is held high during two consecutive TCLK high-to-low transitions (with DSN
low), a bus timeout fault will occur and will be indicated in the appropriate bit in the fault
register. The occurrence of this fault will cause the state sequencer to terminate the
current machine cycle and begin the next. At the end of the current macro-instruction
execution will branch, unless masked, to the machine error interrupt (level 1) software
routine. The DTON signal may be used to override this feature.
DSN
Data Strobe
Active LOW
M/ION
Memory/IO Select
Memory=HIGH
IO=LOW
RD/WN
Read/Write
Select.
Read=HIGH
Write=LOW
Operand/Instruct
Select.
Operand=HIGH
Instr.=LOW
Read Strobe.
Active LOW
O/IN
RDN
WRN
Write Strobe.
Active LOW
RDYN
Ready.
Active LOW
Figure 39: Pin Descriptions
相关PDF资料 |
PDF描述 |
|---|---|
| MA31751 | Memory Management & Block Protection Unit |
| MA31753 | DMA Controller (DMAC) For An MA31750 System |
| MA31755 | 16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| MA3690 | 1553B Bus Controller/Remote Terminal |
| MA3691 | 1553B Bus Controller/Remote Terminal |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MA31751 | 制造商:DYNEX 制造商全称:Dynex Semiconductor 功能描述:Memory Management & Block Protection Unit |
| MA31753 | 制造商:DYNEX 制造商全称:Dynex Semiconductor 功能描述:DMA Controller (DMAC) For An MA31750 System |
| MA31755 | 制造商:DYNEX 制造商全称:Dynex Semiconductor 功能描述:16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| MA318 | 功能描述:CPU与芯片冷却器 INTEL P111 FC-PGA RoHS:否 制造商:ADLINK Technology 尺寸: 电压额定值: 功率额定值: 速度: 气流: 系列: |
| MA3180 | 制造商:PANASONIC 制造商全称:Panasonic Semiconductor 功能描述:Silicon planar type |
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