参数资料
型号: MAX17007GTI+T
厂商: Maxim Integrated Products
文件页数: 13/35页
文件大小: 0K
描述: IC CTRLR QPWM GRAPHICS 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 电源
电流 - 电源: 1.7mA
电源电压: 4.5 V ~ 26 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(4x4)
包装: 带卷 (TR)
Dual and Combinable QPWM Graphics
Core Controllers for Notebook Computers
Pin Description (continued)
PIN
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
EP
NAME
LX1
BST1
GND
DL1
V DD
DL2
PGND
BST2
LX2
DH2
PGOOD2
EN2
CSH2
CSL2
FB2
PAD
FUNCTION
Inductor Connection for SMPS1. Connect LX1 to the switched side of the inductor. LX1 serves as the
lower supply rail for the DH1 high-side gate driver.
Bootstrap Capacitor Connection for SMPS1. The MAX17007/MAX17008 include an internal boost
switch/diode connected between V DD and BST1. Connect to an external capacitor as shown in Figure 1.
Ground. Analog and power ground connection for the low-side gate driver of SMPS1.
Low-Side Gate Driver Output for SMPS1. DL1 swings from GND to V DD . DL1 is forced low after the shutdown
sequence has completed. DL1 is also forced high when an output overvoltage fault is detected, overriding any
negative current-limit condition that may be present. DL1 is forced low in V CC UVLO.
5V Driver Supply Input. Connect V DD to V CC through a 10 resistor. Bypass to ground through a 1μF or
greater ceramic capacitor. V DD is internally connected to the BST diodes and the low-side gate drivers.
Low-Side Gate-Driver Output for SMPS2. DL2 swings from PGND to V DD . DL2 is forced low after the
shutdown sequence has completed. DL2 is also forced high when an output overvoltage fault is
detected, overriding any negative current-limit condition that may be present. DL2 is forced low in V CC
UVLO.
Power Ground for the Low-Side Gate Driver of SMPS2
Bootstrap Capacitor Connection for SMPS2. The MAX17007/MAX17008 include an internal boost switch/
diode connected between V DD and BST2. Connect to an external capacitor as shown in Figure 1.
Inductor Connection for SMPS2. Connect LX2 to the switched side of the inductor. LX2 serves as the
lower supply rail for the DH2 high-side gate driver.
High-Side Gate-Driver Output for SMPS2. DH2 swings from LX2 to BST2. DH2 is low in shutdown.
Open-Drain Power-Good Output for SMPS2. PGOOD2 is low when the FB2 voltage is more than 100mV
below or 150mV above the target voltage, during soft-start, and in shutdown. After the SMPS2 soft-start
circuit has terminated, PGOOD2 becomes high impedance 200μs after the output is in regulation.
In combined mode, PGOOD2 is not used and can be left open.
SMPS2 Enable Input. Connect to V CC for normal operation. Pull EN2 low to disable SMPS2. The controller
slowly ramps down the output voltage to ground, and after the target voltage reaches 0.1V, the controller
forces DL2 low. When both EN1 and EN2 are low, the device enters the low-power shutdown state.
In combined mode, EN2 is not used and should be connected to GND.
Positive Current-Sense Input for SMPS2. Connect to the positive terminal of the current-sense element.
Figure 14 describes two different current-sensing options—using accurate sense resistors or lossless
inductor DCR sensing.
Output-Sense and Negative Current-Sense Input for SMPS2. When using the internal preset 1.5V
feedback divider (FB2 = REF), the controller uses CSL2 to sense the output voltage. Connect to the
negative terminal of the current-sense element. Figure 14 describes two different current-sensing
options—using accurate sense resistors or lossless inductor DCR sensing.
SMPS2 Feedback Input. Adjust the SMPS2 voltage with a resistive voltage-divider between SMPS2 output
and GND. Connect FB2 to REF for preset 1.5V output. Tie FB2 to V CC to configure the
MAX17007/MAX17008 for combined-mode operation.
Exposed Backside Pad. Connect to analog ground.
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