参数资料
型号: MAX17007GTI+T
厂商: Maxim Integrated Products
文件页数: 27/35页
文件大小: 0K
描述: IC CTRLR QPWM GRAPHICS 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 电源
电流 - 电源: 1.7mA
电源电压: 4.5 V ~ 26 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(4x4)
包装: 带卷 (TR)
Dual and Combinable QPWM Graphics
Core Controllers for Notebook Computers
Undervoltage Protection (UVP)
When the feedback voltage drops below the undervolt-
age threshold, the controller immediately pulls PGOOD
low and triggers a 200μs one-shot timer. If the feed-
back voltage remains below the undervoltage fault
threshold for the entire 200μs, then the undervoltage
fault latch of the faulted SMPS is set and that SMPS
begins its shutdown sequence. When the internal target
voltage drops below 0.1V, the MAX17007/MAX17008
force DL low for the faulted SMPS. Toggle EN or cycle
V CC power below V CC POR to clear the fault latch and
restart the controller.
The undervoltage thresholds are -200mV for SMPS1
(fixed 1.05V and adjustable REFIN1), -200mV for
SMPS2 in preset mode (fixed 1.5V output), and -100mV
for SMPS2 in adjustable mode (0.7V feedback).
A UV fault on one side does not affect the other side.
Thermal-Fault Protection (T SHDN )
The MAX17007/MAX17008 feature a thermal-fault pro-
tection circuit. When the junction temperature rises
above +160°C, a thermal sensor activates the fault
latch, pulls PGOOD low, and shuts down the controller.
Both DL and DH are pulled low. Toggle EN or cycle
V CC power below V CC POR to reactivate the controller
after the junction temperature cools by 15°C.
V CC POR and UVLO
Each SMPS of the MAX17007/MAX17008 is enabled
when its respective EN is driven high. On the first rising
EN, the reference powers up first. Once the reference
exceeds its undervoltage lockout (UVLO) threshold
(~ 60μs), the internal analog blocks are turned on and
masked by a 140μs one-shot delay in order to allow the
bias circuitry and analog blocks enough time to settle
to their proper states. With the control circuitry reliably
powered up, the PWM controller begins switching. The
second rising EN, if controlled separately, also has the
140μs one-shot delay before its first DH pulse.
Power-on reset (POR) occurs when V CC rises above
approximately 3V, resetting the fault latch and preparing
the controller for operation. The V CC UVLO circuitry
inhibits switching until V CC rises above 4.25V. The con-
troller powers up the reference once the system enables
the controller, V CC exceeds 4.25V, and either EN is dri-
ven high. With the reference in regulation, the controller
ramps the output voltage to the target voltage with a
1.3mV/μs slew rate for SMPS1 and 0.65mV/μs for SMPS2.
If the V CC voltage drops below 4.25V, the controller
assumes that there is not enough supply voltage to make
valid decisions. To protect the output from overvoltage
faults, the controller shuts down immediately and forces
a high-impedance output (DL and DH pulled low).
Table 4. Fault Protection and Shutdown Operation
MODE
Shutdown (EN_ = High to Low)
Output UVP (Latched)
Thermal Fault (Latched)
Output OVP (Latched)
V CC UVLO Falling Edge
V CC UVLO Rising Edge
V CC POR
CONTROLLER STATE
Voltage soft-shutdown initiated. Error
amplifier target slowly ramped down to
GND.
Controller shuts down and internal target
slews down. Controller remains off until
EN_ toggled or V CC power cycled.
Controller shuts down and the internal
target slews down. Controller remains off
until V CC rises back above UVLO threshold.
SMPS controller enabled (assuming EN_
pulled high).
SMPS inactive.
DRIVER STATE
DL_ low and DH_ low after soft-shutdown
completed, internal 10 discharge on CSL_
activated.
(T 0 1V )
DL_ immediately forced high, DH_ pulled low
(high-side MOSFET disabled).
DL_ low, DH_ low, internal 10 discharge on
CSL_ activated.
DL_, DH_ switching.
DL_ low.
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