参数资料
型号: MAX17007GTI+T
厂商: Maxim Integrated Products
文件页数: 31/35页
文件大小: 0K
描述: IC CTRLR QPWM GRAPHICS 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 电源
电流 - 电源: 1.7mA
电源电压: 4.5 V ~ 26 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(4x4)
包装: 带卷 (TR)
Dual and Combinable QPWM Graphics
Core Controllers for Notebook Computers
I LOAD 12 V OUT 1 ( V IN ? V OUT 1 ) + I LOAD 22 V OUT 2 ( V IN ? V OUT 2 )
I RMS = ? LOAD ? 2 V OUT ( V IN ? V OUT )
? ( I LOAD ) R DS ( ON )
PD ( NH Re sistive ) = ?
When  only  using  ceramic  output  capacitors,  output
overshoot (V SOAR ) typically determines the minimum
output capacitance requirement. Their relatively low
capacitance value can allow significant output over-
shoot when stepping from full-load to no-load condi-
tions, unless designed with a small inductance value
and high switching frequency to minimize the energy
transferred from the inductor to the capacitor during
load-step recovery.
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and feedback
loop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is
not enough voltage ramp in the output voltage signal.
This “fools” the error comparator into triggering a new
cycle immediately after the minimum off-time period
has expired. Double pulsing is more annoying than
harmful, resulting in nothing worse than increased out-
put ripple. However, it can indicate the possible pres-
ence of loop instability due to insufficient ESR. Loop
instability can result in oscillations at the output after
line or load steps. Such perturbations are usually
damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (I RMS ) imposed by the switching currents.
The I RMS requirements can be determined by the fol-
lowing equation for a single-phase application:
I RMS =
V IN
In combined mode, the input RMS current simplifies to:
? I ?
? 2 V IN ?
where I LOAD is the combined output current of both
phases.
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due to their
resistance to inrush surge currents typical of systems
with a mechanical switch or connector in series with the
input. If the Quick-PWM controller is operated as the
second stage of a two-stage power-conversion system,
tantalum input capacitors are acceptable. In either con-
figuration, choose an input capacitor that exhibits less
than +10°C temperature rise at the RMS input current
for optimal circuit longevity.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
The high-side MOSFET (N H ) must be able to dissipate
the resistive losses plus the switching losses at both
V IN(MIN) and V IN(MAX) . Calculate both of these sums.
Ideally, the losses at V IN(MIN) should be roughly equal to
losses at V IN(MAX) , with lower losses in between. If the
losses at V IN(MIN) are significantly higher than the losses
at V IN(MAX) , consider increasing the size of N H (reducing
R DS(ON) but with higher C GATE ). Conversely, if the loss-
es at V IN(MAX) are significantly higher than the losses at
V IN(MIN) , consider reducing the size of N H (increasing
R DS(ON) to lower C GATE ). If V IN does not vary over a
wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
Choose a low-side MOSFET that has the lowest possible
on-resistance (R DS(ON) ), comes in a moderate-sized
package (i.e., one or two 8-pin SOs, DPAK, or D 2 PAK),
and is reasonably priced. Make sure that the DL gate
driver can supply sufficient current to support the gate
charge and the current injected into the parasitic gate-
to-drain capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems might
occur (see the MOSFET Gate Drivers (DH, DL) section).
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N H ), the worst-
case power dissipation due to resistance occurs at the
minimum input voltage:
? V OUT ? 2
? V IN ( MIN ) ?
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R DS(ON) required to stay within package
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (R DS(ON) ) losses. High-
side switching losses do not usually become an issue
until the input is greater than approximately 15V.
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