参数资料
型号: MAX17007GTI+T
厂商: Maxim Integrated Products
文件页数: 33/35页
文件大小: 0K
描述: IC CTRLR QPWM GRAPHICS 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 电源
电流 - 电源: 1.7mA
电源电压: 4.5 V ~ 26 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(4x4)
包装: 带卷 (TR)
Dual and Combinable QPWM Graphics
Core Controllers for Notebook Computers
? V
? ?
V IN ( MIN ) = ?
?
(
)
? 1 ? h × t OFF ( MIN ) f SW
?
?
In  a  single-phase  configuration,  the  absolute  point  of
dropout is when the inductor current ramps down dur-
ing the minimum off-time ( ? I DOWN ) as much as it ramps
up during the on-time ( ? I UP ). The ratio h = ? I UP /
? I DOWN is an indicator of the ability to slew the inductor
current higher in response to increased load and must
always be greater than 1. As h approaches 1 —the
absolute minimum dropout point—the inductor current
cannot increase as much during each switching cycle,
and V SAG greatly increases unless additional output
capacitance is used. A reasonable minimum value for h
is 1.5, but adjusting this up or down allows trade-offs
between V SAG , output capacitance, and minimum
operating voltage. For a given value of h, the minimum
operating voltage can be calculated as:
V OUT CHG
?
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Follow these guidelines for good PCB layout:
? Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
? Connect all analog grounds to a separate solid
copper plane, which connects to the GND pin of
the Quick-PWM controller. This includes the V CC
bypass capacitor, REF bypass capacitors, REFIN1
components, and feedback compensation/dividers.
? Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCBs (2oz vs. 1oz) can enhance full-load
V IN ( MIN ) = ?
? = 1 . 86 V
where V CHG is the parasitic voltage drop in the charge
path (see the On-Time One-Shot section), and t OFF(MIN)
is from the Electrical Characteristics table. The absolute
minimum input voltage is calculated with h = 1.
If the calculated V IN(MIN) is greater than the required min-
imum input voltage, then reduce the operating frequency
or add output capacitance to obtain an acceptable V SAG .
If operation near dropout is anticipated, calculate V SAG to
be sure of adequate transient response.
Dropout Design Example:
V OUT = 1.5V
f SW = 300kHz
t OFF(MIN) = 250ns
V CHG = 150mV (10A load)
h = 1.5
? 1 . 5 V + 150 mV ?
? 1 ? ( 0 . 25 μ s × 1 . 5 × 300 kHz ) ?
?
?
?
efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single
m ? of excess trace resistance causes a measur-
able efficiency penalty.
Keep the high current, gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
Route high-speed switching nodes away from sensi-
tive analog areas (REF, REFIN1, FB2, CSH, and CSL).
V IN ( MIN ) = ?
? = 1 . 78 V
Calculating again with h = 1 gives the absolute limit of
dropout:
? 1 . 5 V + 150 mV ?
? 1 ? ( 0 . 25 μ s × 1 . 0 × 300 kHz ) ?
Therefore, V IN must be greater than 1.78V, even with
very large output capacitance, and a practical input volt-
age with reasonable output capacitance would be 2.0V.
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (low-side MOSFET source, C IN ,
C OUT , and anode of the low-side Schottky). If possi-
ble, make all these connections on the top layer
with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is 1in
from the controller IC).
______________________________________________________________________________________
33
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