参数资料
型号: MAX17101ETJ+T
厂商: Maxim Integrated Products
文件页数: 14/31页
文件大小: 0K
描述: IC REG CTRLR DIV PWM CM 32TQFNEP
标准包装: 2,500
PWM 型: 电流模式
输出数: 3
频率 - 最大: 500kHz
电源电压: 6 V ~ 24 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
Dual Quick-PWM, Step-Down Controller
with Low-Power LDO, RTC Regulator
Pin Description (continued)
PIN
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NAME
ON1
DH1
LX1
BST1
DL1
V DD
SECFB
AGND
PGND
DL2
BST2
LX2
DH2
ON2
PGOOD2
SKIP
OUT2
ILIM2
REFIN2
EP
FUNCTION
Enable Input for SMPS1. Drive ON1 high to enable SMPS1. Drive ON1 low to shut down SMPS1.
High-Side Gate-Driver Output for SMPS1. DH1 swings from LX1 to BST1.
Inductor Connection for SMPS1. Connect LX1 to the switched side of the inductor. LX1 is the lower supply
rail for the DH1 high-side gate driver.
Boost Flying-Capacitor Connection for SMPS1. Connect to an external capacitor as shown in Figure 1. An
optional resistor in series with BST1 allows the DH1 turn-on current to be adjusted.
Low-Side Gate-Driver Output for SMPS1. DL1 swings from PGND to V DD.
Supply-Voltage Input for the DL_ Gate Drivers. Connect to a 5V supply. Also connect to the drain of the
BST diode switch.
Secondary Feedback Input. The secondary feedback input forces the SMPS1 output into ultrasonic mode
when the SECFB voltage drops below its 2V threshold voltage. This forces DL1 and DH1 to switch,
allowing the system to refresh an external low-power charge pump being driven by DL1 (see Figure 1 for
the Standard Application Circuit—Main Supply ). Connect SECFB to V CC (the 5V bias supply) to disable
secondary feedback.
Analog Ground. Connect backside exposed pad to AGND.
Power Ground
Low-Side Gate-Driver Output for SMPS2. DL2 swings from PGND to V DD.
Boost Flying-Capacitor Connection for SMPS2. Connect to an external capacitor as shown in Figure 1. An
optional resistor in series with BST2 allows the DH2 turn-on current to be adjusted.
Inductor Connection for SMPS2. Connect LX2 to the switched side of the inductor. LX2 is the lower supply
rail for the DH2 high-side gate driver.
High-Side Gate-Driver Output for SMPS2. DH2 swings from LX2 to BST2.
Enable Input for SMPS2. Drive ON2 high to enable SMPS2. Drive ON2 low to shut down SMPS2.
Open-Drain Power-Good Output for SMPS2. PGOOD2 is low when the output voltage is more than 150mV
(typ) below the REFIN2 voltage or more than 16% below the preset voltage, during soft-start, in shutdown,
and when the fault latch has been tripped. After the soft-start circuit has terminated, PGOOD2 becomes
high impedance if the output is in regulation. PGOOD2 is blanked—forced high-impedance state—when a
dynamic REFIN transition is detected.
Pulse-Skipping Control Input. This three-level input determines the operating mode for the switching
regulators:
High (V CC ) = forced-PWM operation
Open/REF (2V) = ultrasonic mode
GND = pulse-skipping mode
Output Voltage-Sense Input for SMPS2. OUT2 is an input to the Quick-PWM on-time one-shot timer. OUT2
also serves as the feedback input for the preset 3.3V (REFIN2 = V CC ) and 1.05V (REFIN2 = RTC).
Valley Current-Limit Adjustment for SMPS2. The GND - LX2 current-limit threshold is 1/10 the voltage
present on ILIM2 over a 0.2V to 2V range. An internal 5 μA current source allows this voltage to be set with
a single resistor between ILIM2 and analog ground.
External Reference Input for SMPS2. REFIN2 sets the feedback-regulation voltage (V OUT2 = V REFIN2 ).
Connect REFIN2 to RTC for fixed 1.05V operation. Connect REFIN2 to V CC for fixed 3.3V operation.
Exposed Pad. Connect the backside exposed pad to AGND.
14
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