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参数资料
| 型号： | MAX17101ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/31页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR DIV PWM CM 32TQFNEP |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 3 |
| 频率 - 最大： | 500kHz |
| 电源电压： | 6 V ~ 24 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 是 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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Dual Quick-PWM, Step-Down Controller
with Low-Power LDO, RTC Regulator
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO, RTC, OUT1, OUT2, and REF, V IN = 12V, V DD = V CC = V SECFB = 5V, V REFIN2 = 1.0V, BYP =
LDOSEL = GND, ONLDO = IN, ON1 = ON2 = V CC , T A = -40°C to +85°C , unless otherwise noted.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUT2 Undervoltage-Protection
Trip Threshold
PGOOD2 Lower Trip Threshold
PGOOD2 Output-Low Voltage
V UVP(OUT2) With respect to error-comparator threshold
With respect to error-comparator threshold,
falling edge, hysteresis = 2%
V OUT2 = V REFIN2 - 150mV (PGOOD2 low
impedance), I SINK = 4mA
60
-20
80
-10
0.4
%
%
V
CURRENT LIMIT
ILIM_ Adjustment Range
V ILIM
0.2
2.0
V
Valley Current-Limit Threshold
(Adjustable)
V VALLEY
V AGND - V LX _
R ILIM _ = 100k
R ILIM _ = 200k
40
85
60
115
mV
GATE DRIVERS
DH_ Gate Driver On-Resistance
DL_ Gate Driver On-Resistance
R DH
R DL
BST1 - LX1 and BST2 - LX2 forced to 5V
DL1, DL2; high state
DL1, DL2; low state
3.5
4.5
1.5
INPUTS AND OUTPUTS
TON Input Logic Levels
High
REF or open
V CC -
0.4V
1.6
3.0
V
Low
0.4
SKIP Input Logic Levels
High (forced PWM)
Open (ultrasonic)
V CC -
0.4V
1.6
3.0
V
Low (skip)
0.4
ON_ Input Logic Levels
ONLDO Input Logic Levels
High (SMPS on)
Low (SMPS off)
High (SMPS on)
Low (SMPS off)
2.4
2.4
0.8
0.8
V
V
Note 1: DC output accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduc-
tion, the MAX17101 regulates the valley of the output ripple, so the actual DC output voltage is higher than the trip level by
50% of the output ripple voltage. In discontinuous conduction (I OUT < I LOAD(SKIP) ), the output voltage has a DC regulation
level higher than the error-comparator threshold by approximately 1.5% due to slope compensation.
Note 2: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = PGND, VBST = 5V,
and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times might be differ-
ent due to MOSFET switching speeds.
Note 3: Specifications to T A = -40°C are guaranteed by design and not production tested.
Note 4: Specifications increased by 1 Ω to account for test measurement error.
_______________________________________________________________________________________
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