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参数资料
| 型号： | MAX17101ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 22/31页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR DIV PWM CM 32TQFNEP |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 3 |
| 频率 - 最大： | 500kHz |
| 电源电压： | 6 V ~ 24 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 是 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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Dual Quick-PWM, Step-Down Controller
with Low-Power LDO, RTC Regulator
V OUT ( PWM ) = V NOM + ? RIPPLE ?
Automatic Fault Blanking
When the MAX17101 automatically detects that the
internal target and REFIN2 are more than ±25mV (typ)
apart, the controller automatically blanks PGOOD2,
blanks the UVP protection, and sets the OVP threshold
to REF + 200mV. The blanking remains until 1) the
internal target and REFIN2 are within ±20mV of each
other and 2) an edge is detected on the error amplifier
signifying that the output is in regulation. This prevents
the system or internal fault protection from shutting
down the controller during transitions.
Valley Current-Limit Protection
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that senses the inductor current
through the low-side MOSFET—across LX to AGND. If
the current through the low-side MOSFET exceeds the
valley current-limit threshold, the PWM controller is not
allowed to initiate a new cycle. The actual peak current
is greater than the valley current-limit threshold by an
amount equal to the inductor ripple current. Therefore,
the exact current-limit characteristic and maximum load
capability are a function of the inductor value and bat-
tery voltage. When combined with the undervoltage
protection circuit, this current-limit method is effective
in almost every circumstance.
In forced-PWM mode, the MAX17101 also implements
a negative current limit to prevent excessive reverse
inductor currents when V OUT is sinking current. The
negative current-limit threshold is set to approximately
120% of the positive current limit.
POR, UVLO
When V CC rises above the power-on reset (POR) thresh-
old, the MAX17101 clears the fault latches, forces the
low-side MOSFET to turn on (DL high), and resets the
soft-start circuit, preparing the controller for power-up.
However, the V CC undervoltage lockout (UVLO) circuitry
inhibits switching until V CC reaches 4.2V (typ). When
V CC rises above 4.2V and the controller has been
enabled (ON_ pulled high), the controller activates the
enabled PWM controllers and initializes soft-start.
When V CC drops below the UVLO threshold (falling
edge), the controller stops switching, and DH and DL are
pulled low and a 10 Ω switch discharges the outputs.
When the 2V POR falling-edge threshold is reached, the
DL state no longer matters since there is not enough volt-
age to force the switching MOSFETs into a low on-resis-
tance state, so the controller pulls DL high, allowing a soft
discharge of the output capacitors (damped response).
However, if the V CC recovers before reaching the falling
POR threshold, DL remains low until the error comparator
has been properly powered up and triggers an on-time.
Only one enable input needs to be toggled to clear the
fault latches and activate both outputs.
Soft-Start and Soft-Shutdown
The MAX17101 includes voltage soft-start and soft-
shutdown —slowly ramping up and down the target
voltage. During startup, the slew-rate control softly
slews the preset/fixed target voltage over a 1ms startup
period or its tracking voltage (REFIN2 < 2V) with a
1mV/μs slew rate. This long startup period reduces the
inrush current during startup.
When ON1 or ON2 is pulled low or the output undervolt-
age fault latch is set, the respective output automatically
enters soft-shutdown—the regulator enters PWM mode
and ramps down its preset/fixed output voltage over a
1ms period or its tracking voltage (REFIN2 < 2V) with a
1mV/μs slew rate. After the output voltage drops below
0.1V, the MAX17101 pulls DL high, clamping the output
and LX switching node to ground, preventing leakage
currents from pulling up the output and minimizing the
negative output-voltage undershoot during shutdown.
Output Voltage
DC output-accuracy specifications in the Electrical
Characteristics table refer to the error comparator’s
threshold. When the inductor continuously conducts, the
MAX17101 regulates the valley of the output ripple, so
the actual DC output voltage is lower than the slope-com-
pensated trip level by 50% of the output ripple voltage.
For PWM operation (continuous conduction), the output
voltage is accurately defined by the following equation:
? V ?
? 2 A CCV ?
where V NOM is the nominal feedback voltage, A CCV is
the integrator’s gain, and V RIPPLE is the output ripple
voltage (V RIPPLE = ESR x Δ I INDUCTOR , as described in
the Output Capacitor Selection section).
In discontinuous conduction (I OUT < I LOAD(SKIP) ), the
longer off-times allow the slope compensation to
increase the threshold voltage by as much as 1%, so
the output voltage regulates slightly higher than it
would in PWM operation.
Internal Integrator
The internal integrator improves the output accuracy by
removing any output accuracy errors caused by the
slope compensation, output ripple voltage, and error-
amplifier offset. Therefore, the DC accuracy (in forced-
PWM mode) depends on the integrator’s gain, the inte-
grator’s offset, and the accuracy of the integrator’s refe-
rence input.
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