参数资料
型号: MAX3109ETJ+
厂商: Maxim Integrated Products
文件页数: 11/66页
文件大小: 0K
描述: SEMICONDUCTOR OTHER
标准包装: 60
系列: *
Dual Serial UART with 128-Word FIFOs
MAX3109
19
Maxim Integrated
Clock Selection
The MAX3109 can be clocked by either an external
crystal or an external clock source. Figure 7 shows a
simplified diagram of the clock selection circuitry. When
the MAX3109 is clocked by a crystal, the STSInt[5]:
ClkReady bit indicates when the crystal oscillator has
reached steady state and the baud-rate generator is
ready for stable operation.
Each UART baud rate can be individually programmed
and both share the same reference clock input.
The baud-rate clock can be routed to the RTS_ output by
setting the CLKSource[7]: CLKtoRTS bit high. The clock
rate is 16x the baud rate in standard operating mode, 8x
the baud rate in 2x rate mode, and 4x the baud rate in 4x
rate mode. If the fractional portion of the baud-rate gen-
erator is used, the clock is not regular and exhibits jitter.
Crystal Oscillator
The MAX3109 is equipped with a crystal oscillator to pro-
vide high baud-rate accuracy and low power consump-
tion. Set the CLKSource[1]: CrystalEn bit high to enable
and select the crystal oscillator. The on-chip crystal
oscillator has integrated load capacitances of 16pF in
both the XIN and XOUT pins. Connect only an external
crystal or ceramic oscillator between XIN and XOUT.
External Clock Source
Connect an external single-ended clock source to XIN
when not using the crystal oscillator. Leave XOUT uncon-
nected. Set the CLKSource[1]: CrystalEn bit low to
select external clocking.
PLL and Predivider
The internal predivider and PLL allow for compatibility with
a wide range of external clock frequencies and baud rates.
The PLL can be configured to multiply the input clock
rate by a factor of 6, 48, 96, or 144 by the PLLConfig[7:6]
bits. The predivider is located between the input clock
and the PLL and allows division of the input clock by an
integer factor between 1 and 63. This value is defined
by the PLLConfig[5:0] bits. See the PLLConfig register
description for more information. Use of the PLL requires
VCC to be higher than 2.35V.
Fractional Baud-Rate Generators
Each UART has an internal fractional baud-rate gen-
erator that provides a high degree of flexibility and high
resolution in baud-rate programming. The baud-rate
generator has a 16-bit integer divisor and a 4-bit word for
the fractional divisor. The fractional baud-rate generator
can be used either with the crystal oscillator or external
clock source.
The integer and fractional divisors are calculated by the
divisor, D:
×
=
×
REF
f
RateMode
D
16 BaudRate
where fREF is the reference frequency input to the baud-
rate generator, RateMode is the rate mode multiplier (1x
default), BaudRate is the desired baud rate, and D is the
ideal divisor. fREF must be less than 96MHz. RateMode
is 1 in 1x rate mode, 2 in 2x rate mode, and 4 in 4x rate
mode.
The integer divisor portion, DIV, of the divisor, D, is
obtained by truncating D:
DIV = TRUNC(D)
DIV can be a maximum of 16 bits (65,535) wide and
is programmed into the two single-byte-wide registers
DIVMSB and DIVLSB. The minimum allowed value for
DIVLSB is 1.
The fractional portion of the divisor, FRACT, is a 4-bit
nibble that is programmed into BRGConfig[3:0]. The
maximum value is 15, allowing the divisor to be pro-
grammed with a resolution of 0.0625. FRACT is calcu-
lated as: FRACT = ROUND(16 x (D - DIV)).
Figure 7. Clock Selection Diagram
CRYSTAL
OSCILLATOR
XOUT
CrystalEn
XIN
FRACTIONAL
BAUD-RATE
GENERATOR 0
FRACTIONAL
BAUD-RATE
GENERATOR 1
PLLBypass
PLLEn
PLL
DIVIDER
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