参数资料
型号: MAX3109ETJ+
厂商: Maxim Integrated Products
文件页数: 7/66页
文件大小: 0K
描述: SEMICONDUCTOR OTHER
标准包装: 60
系列: *
Dual Serial UART with 128-Word FIFOs
MAX3109
15
Maxim Integrated
Pin Description (continued)
PIN
NAME
FUNCTION
8
VL
Digital Interface Power Supply. VL powers the internal logic-level translators for RST, IRQ, MOSI/A1, CS/A0,
SCLK/SCL, MISO/SDA, LDOEN, and SPI/I2C. Bypass VL with a 0.1FF ceramic capacitor to DGND.
9
SPI/I2C
SPI Selector Input or Active-Low I2C. Drive SPI/I2C low to enable I2C. Drive SPI/I2C high to enable SPI.
10
DGND
Digital Ground
11
GPIO0
General-Purpose Input/Output 0. GPIO0 is user-programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO0 has a weak pulldown resistor to DGND when
configured as an input. GPIO0 is the reference clock output when bit 7 of the TxSynch register is set to
high (see the UART Clock to GPIO section for more information).
12
GPIO4
General-Purpose Input/Output 4. GPIO4 is user-programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO4 has a weak pulldown resistor to DGND when
configured as an input. GPIO4 is the reference clock output when bit 7 of the TxSynch register is set to
high (see the UART Clock to GPIO section for more information).
13
GPIO1
General-Purpose Input/Output 1. GPIO1 is user-programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO1 has a weak pulldown resistor to DGND when
configured as an input. GPIO1 is the TIMER output when bit 7 of the TIMER2 register is set high.
14
GPIO5
General-Purpose Input/Output 5. GPIO5 is user-programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO5 has a weak pulldown resistor to DGND when
configured as an input. GPIO5 is the TIMER output when bit 7 of the TIMER2 register is set high.
15
CTS0
Active-Low Clear-to-Send Input for UART0. CTS0 is a flow-control status input.
16
CTS1
Active-Low Clear-to-Send Input for UART1. CTS1 is a flow-control status input.
17
TX1
Serial Transmitting Data Output for UART1. TX1 is logic-high when RST is low or when the externally
supplied V18 is not powered.
18
TX0
Serial Transmitting Data Output for UART0. TX0 is logic-high when RST is low or when the externally
supplied V18 is not powered.
19
RX0
Serial Receiving Data Input for UART0. RX0 has an internal weak pullup resistor to VEXT.
20
RX1
Serial Receiving Data Input for UART1. RX1 has an internal weak pullup resistor to VEXT.
21
RTS0
Active-Low Request-to-Send Output for UART0. RTS0 can be set high or low by programming the LCR
register. RTS0 is the UART system clock/fractional divider output when bit 7 of the CLKSource register is
set high. RTS0 is logic-high when RST is low or when the externally supplied V18 is not powered.
22
RTS1
Active-Low Request-to-Send Output for UART1. RTS1 can be set high or low by programming the LCR
register. RTS1 is the UART system clock/fractional divider output when bit 7 of the CLKSource register is
set high. RTS1 is logic-high when RST is low or when the externally supplied V18 is not powered.
23
GPIO2
General-Purpose Input/Output 2. GPIO2 is user-programmable as input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO2 has a weak pulldown resistor to DGND when
configured as an input.
24
GPIO3
General-Purpose Input/Output 3. GPIO3 is user-programmable as input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO3 has a weak pulldown resistor to DGND when
configured as an input.
25
VEXT
Transceiver Interface Power Supply. VEXT powers the internal logic-level translators for RX_, TX_, RTS_,
CTS_, and GPIO_. Bypass VEXT with a 0.1FF ceramic capacitor to DGND.
26
XIN
Crystal/Clock Input. When using an external crystal, connect one end of the crystal to XIN and the other
end to XOUT. When using an external clock source, drive XIN with the single-ended external clock.
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