参数资料
型号: MAX3109ETJ+
厂商: Maxim Integrated Products
文件页数: 14/66页
文件大小: 0K
描述: SEMICONDUCTOR OTHER
标准包装: 60
系列: *
Dual Serial UART with 128-Word FIFOs
MAX3109
21
Maxim Integrated
UART Clock to GPIO
The MAX3109 reference clock can be routed to the
GPIO0 and/or GPIO4 outputs if a synchronous high-
frequency clock is needed by another device. Enable
routing a UART clock to GPIO0 and/or GPIO4 in the
TxSynch register. This output clock could, for example,
be used to clock another UART device.
Multidrop Mode
In multidrop mode, also known as 9-bit mode, the data
word length is 8 bits and a 9th bit is used for distin-
guishing between an address word and a data word.
Multidrop mode is enabled by the MODE2[6]: MultiDrop
bit. The MultiDrop bit takes the place of the parity bit in
the data word structure. Parity checking is disabled and
an interrupt is generated in SpclCharInt[5]: MultiDropInt
when an address (9th bit is 1) is received while in multi-
drop mode.
It is up to the host processor to filter out the data intended
for its address. Alternatively, the auto data-filtering fea-
ture can be used to automatically filter out the data not
intended for the station’s specific 9-bit mode address.
Auto Data Filtering in Multidrop Mode
In multidrop mode, the MAX3109 can be configured
to automatically filter out data that is not meant for its
address. The address is user-definable either by pro-
gramming a register value or a combination of a register
value and GPIO hardware inputs. Use either the entire
XOFF2 register or the XOFF2[7:4] bits in combination
with GPIO_ inputs to define the address.
Enable multidrop mode by setting the MODE2[6]:
MultiDrop bit high and enable auto data filtering by set-
ting the MODE2[4]: SpecialChr bit high.
When using register bits in combination with GPIO_ inputs
to define the address, the MSB of the address is written
to the XOFF2[7:4] bits, while the LSBs of the address are
defined by the GPIOs. To enable this address-definition
method along with auto data filtering, set the FlowCtrl[2]:
GPIAddr bit high in addition to the MODE2[4]: SpecialChr
and MODE2[6]: MultiDrop bits. The GPIO_ inputs are
automatically read when the FlowCtrl[2]: GPIAddr bit is
set high, and the address is automatically updated on
logic changes to any GPIO pin.
When using auto data filtering, the MAX3109 checks
each received address against the programmed station
address. When an address is received that matches
the station’s address, received data is stored in the
RxFIFO. When an address is received that does not
match the station’s address, received data is discarded.
Addresses are not stored into the FIFO but an inter-
rupt is still generated in SpclCharInt[5]: MultiDropInt
upon receiving an address. An additional interrupt is
generated in SpclCharInt[3]: XOFF2Int when the station
address is received.
Auto Transceiver Direction Control
In some half-duplex communication systems, the trans-
ceiver’s transmitter must be turned off when data is
being received in order to not load the bus. This is the
case in half-duplex RS-485 communication. Similarly, in
full-duplex multidrop communication such as RS-485 or
RS-422 V.11, only one transmitter can be enabled at any
one time while the others must be disabled. The MAX3109
can automatically enable/disable a transceiver’s transmit-
ter and/or receiver at the hardware level by controlling its
DE and RE pins. This feature relieves the host processor
of this time-critical task.
The RTS_ output is used to control the transceivers’
transmit-enable input and is automatically set high
when the MAX3109’s transmitter starts transmission.
This occurs as soon as data is present in the transmit
FIFO. Auto transceiver direction control is enabled by
the MODE1[4]: TrnscvCtrl bit. Figure 10 shows a typical
MAX3109 connection in an RS-485 application using the
auto transceiver direction control feature.
The RTS output can be set high in advance of TX_
transmission by a programmable time period called the
setup time (Figure 11). The setup time is programmed
by the HDplxDelay[7:4]: Setupx bits. Similarly, the RTS_
output can be held high for a programmable period
after the transmitter has completed transmission called
the hold time. The hold time is programmed by the
HDplxDelay[3:0] bits.
Transmitter Triggering and Synchronization
The MAX3109 allows synchronization of transmitters so
that selected UARTs start transmitting data when a trigger
command is received. Optional delays can also be pro-
grammed that delay the start of transmission after a trig-
ger command is received. A UART’s transmitter can be
assigned one of 16 possible SPI/I2C trigger commands.
A trigger command is defined as any of the 16 special
values written into the GloblComnd register (see the
GloblComnd register description for more information).
When a byte is written into the GloblComnd register, the
UART select bit (U) is ignored by the MAX3109 and the
GloblComnd applies to both UARTs. Transmission is
initiated when the MAX3109 receives an assigned SPI/
I2C trigger command, the selected transmitter is initially
disabled, and data has been loaded into its TxFIFO.
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