参数资料
型号: MAX5073ETI+T
厂商: Maxim Integrated Products
文件页数: 19/25页
文件大小: 0K
描述: IC REG BUCK BST ADJ 1A/2A 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 28 V
输入电压: 4.5 V ~ 23 V
PWM 型: 电压模式
频率 - 开关: 200kHz ~ 2.2MHz
电流 - 输出: 1A,2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 28-TQFN-EP(5x5)
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
put. The high switching frequency of MAX5073 allows
P DC = I RMS × R DS(ON)MAX
P SW = O IN R F SW
2
where V DS is the drop across the internal MOSFET. See
the Electrical Characteristics for the R DS(ON)MAX value.
V × I × ( t + t ) × f
4
where t R and t F are rise and fall times of the internal
MOSFET. The t R and t F are typically 20ns, and can be
measured in the actual application.
The supply current in the MAX5073 is dependent on
the switching frequency. See the Typical Operating
Characteristics to find the supply current of the
MAX5073 at a given operating frequency. The power
dissipation (P S ) in the device due to supply current (I S )
is calculated using following equation.
use of ceramic capacitors at the output.
Choose all the passive power components that meet
the output ripple, component size, and component cost
requirements. Choose the small-signal components for
the error amplifier to achieve the desired closed-loop
bandwidth and phase margin. Use a simple pole-zero
pair (Type II) compensation if the output capacitor ESR
zero frequency is below the unity-gain crossover fre-
quency (f C ). Type III compensation is necessary when
the ESR zero frequency is higher than f C or when com-
pensating for a continuous mode boost converter that
has a right-half-plane zero.
Use the following procedure 1 to calculate the compen-
sation network components when f ZERO,ESR < f C .
Buck Converter Compensation
Procedure 1 (See Figure 6)
1) Calculate the f ZERO,ESR and LC double pole:
P S = V INMAX × I SUPPLY
The total power dissipation P T in the device is:
P T = P DC1 + P DC2 + P SW1 + P SW2 + P S
f ZERO , ESR =
f LC =
1
2 π × ESR × C OUT
1
f C = SW
where P DC1 and P DC2 are DC losses in converter 1 and
converter 2, respectively. P SW1 and P SW2 are switching
losses in converter 1 and converter 2.
Calculate the temperature rise of the die using the
following equation:
T J = T C + (P T x θ JC )
where, θ JC is the junction-to-case thermal impedance of
the package equal to +2 ° C/W. Solder the exposed pad of
the package to a large copper area to minimize the case-
to-ambient thermal impedance. Measure the temperature
of the copper area near the device at a worst-case condi-
tion of power dissipation and use +2 ° C/W as θ JC thermal
impedance. The case-to-ambient thermal impedance
( θ C-A ) is dependent on how well the heat is transferred
from the PC board to the ambient. Use a large copper
area to keep the PC board temperature low. The θ C-A is
usually in the +20 ° C/W to +40 ° C/W range .
Compensation
2 π × L OUT × C OUT
2) Calculate the unity-gain crossover frequency as:
f
20
If the f ZERO,ESR is lower than f C and close to f LC , use a
Type II compensation network where R F C F provides a
midband zero f mid,zero , and R F C CF provides a high-fre-
quency pole.
3) Calculate modulator gain G M at the crossover fre-
quency.
V OUT
R 1
The MAX5073 provides an internal transconductance
amplifier with its inverting input and its output available
-
g M
COMP
to the user for external frequency compensation. The
flexibility of external compensation for each converter
offers wide selection of output filtering components,
especially the output capacitor. For cost-sensitive
R 2
V REF
+
R F
C F
C CF
applications, use high-ESR aluminum electrolytic
capacitors; for component size-sensitive applications,
use low-ESR tantalum or ceramic capacitors at the out-
Figure 6. Type II Compensation Network
______________________________________________________________________________________
19
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