参数资料
型号: MAX5073ETI+T
厂商: Maxim Integrated Products
文件页数: 21/25页
文件大小: 0K
描述: IC REG BUCK BST ADJ 1A/2A 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 28 V
输入电压: 4.5 V ~ 23 V
PWM 型: 电压模式
频率 - 开关: 200kHz ~ 2.2MHz
电流 - 输出: 1A,2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 28-TQFN-EP(5x5)
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
OUTPUT2
PGOOD2
PGOOD1
OUTPUT1
PGND
SGND
OUTPUT1
3.3V/2A
28 27 26 25 24 23 22
2 BST2/VDD2 BST1/VDD1 20
OUTPUT2
12V/0.2A
VL
CLOCK
OUT
SOURCE2 PGND SGND SOURCE1 PGOOD2
1 CLKOUT PGOOD1 21
SGND
EP
3 DRAIN2
DRAIN1 19
VL
INPUT
4 DRAIN2
DRAIN1 18
ON
OFF
5 EN2
MAX5073
EN1 17
ON
OFF
6 FB2
7 COMP2
FB1 16
COMP1 15
SYNC N.C. OSC
8 9 10
V+
11
VL
12
VL BYPASS
13 14
SYSTEM
CLOCK
INPUT
*CONNECT PGND AND SGND TOGETHER AT ONE POINT NEAR
THE RETURN TERMINALS OF THE V+ AND VL BYPASS CAPACITORS.
Figure 8. Buck-Boost Application
V IN
V OUT
Boost Converter Compensation
The boost converter compensation gets complicated
due to the presence of a right-half-plane zero f ZERO,RHP .
The right-half-plane zero causes a drop in-phase while
adding positive (+1) slope to the gain curve. It is impor-
tant to drop the gain significantly below unity before the
RHP frequency. Use the following procedure to calcu-
late the compensation components.
1) Calculate the LC double-pole frequency, F LC , and
the right half plane zero frequency.
where:
D = 1 ?
V OUT
R ( MIN ) =
I OUT ( MAX )
Target the unity-gain crossover frequency for:
f LC =
1 ? D
f C ≤
f ZERO , RHP
5
( 1 ? D ) R ( MIN )
( f Z 1 =
)
2 π × L OUT C OUT
2
f ZERO , RHP =
2 π × L OUT
C F =
where R F ≥ 10k ? .
1
2) Place a zero 2 π × R F × C F at 0.75 x f LC .
1
2 π × 0 . 75 × f LC × R F
______________________________________________________________________________________
21
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