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参数资料
| 型号： | MAX5951ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/25页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 88% |
| 电源电压： | 4.5 V ~ 16 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
12V/5V Input Buck PWM Controller
Pin Description
PIN
1, 5
2
3, 4, 6–11
12
13
14
15
16
17
18
19
20
21
22
23
NAME
IN
PUVLO
N.C.
DCENI
THRESH
AGND
SYNCOUT
SYNCIN
RT
STARTUP
PGOOD
COMP
FB
SENSE
ILIM
FUNCTION
Supply Input Connection. Connect to an external voltage source from 8V to 16V. For 5V input
application, connect IN = REG to a 5V ±10% source. Connect an external divider from IN to PUVLO to
AGND to lower the startup voltage.
PWM UVLO Divider Center Point. Use an external divider to override the internal PWM UVLO divider.
The rising threshold is set to 1.220V with 122mV hysteresis. Leave PUVLO unconnected for the default
PWM UVLO.
No Connection. Do not connect.
DC-DC Enable Input. DCENI must be above V THRESH for the PWM controller to start. Connect to REG
if not used.
DC-DC Enable Input Threshold Set. Connect a resistive divider from REG to THRESH to AGND to set
the DCENI threshold. Connect to ground for a default threshold of 1.220V.
Analog Ground Connection. Solder the exposed pad to a large AGND plane. Connect AGND and
PGND together at one point near the input bypass capacitor return terminal.
Synchronization Output. SYNCOUT is a synchronization signal to drive the SYNCIN of a second
MAX5950 or MAX5951, if used. Leave SYNCOUT unconnected when not used.
Synchronization Input. SYNCIN accepts the SYNCOUT from another MAX5950 or MAX5951 and shifts
switching by 180°, allowing the reduction of the input bypass capacitors. When used, drive with a
frequency at least 20% higher than the frequency programmed through the RT pin. If phase
staggering is desired, use 50% duty cycle. Connect SYNCIN to AGND when not used.
Oscillator Timing Resistor Connection. Connect a 500k ? to 50k ? resistor from RT to AGND to
program the switching frequency from 100kHz to 1MHz.
Startup Input. STARTUP coordinates simultaneous soft-start for multiple converters. See the Tracking
(STARTUP) section.
Power-Good Output. PGOOD output goes high when SENSE is above V REF and STARTUP is high.
Error-Amplifier Output. Connect COMP to the compensation feedback network.
Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter output
to AGND to set the output voltage. The FB voltage regulates to the reference voltage.
Output Voltage Sense. Connect a resistive divider from the converter output to SENSE to AGND to
monitor the programmed output voltage. SENSE is compared to the internal reference, V REF .
Valley Current-Limit Set Output. Connect a 25k ? to 175k ? resistor, R ILIM , from ILIM to AGND to
program the valley current-limit threshold from 50mV to 350mV. ILIM sources 20μA out to R ILIM . The
resulting voltage divided by 10 is the valley current limit. Alternatively, a resistive divider from REG to
ILIM to AGND can be used to set the valley current limit.
10
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