参数资料
型号: MAX5951ETJ+T
厂商: Maxim Integrated Products
文件页数: 14/25页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1MHz
占空比: 88%
电源电压: 4.5 V ~ 16 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
12V/5V Input Buck PWM Controller
Error Amplifier
The output of the internal error amplifier (COMP) is
available for frequency compensation (see the
Compensation Design Guidelines section). The invert-
ing input is FB; the output is COMP. The error amplifier
has an 80dB open-loop gain and a 2.5MHz GBW prod-
uct. See the Typical Operating Characteristics for the
Open-Loop Gain and Phase vs. Frequency graph.
PWM Comparator
An internal ramp is compared against the output of the
error amplifier to generate the PWM signal. The ampli-
tude of the ramp, V RAMP, is 1.8V.
Output Short-Circuit Protection
(Hiccup Mode)
The current-limit circuit employs a lossless valley cur-
rent-limiting algorithm that uses the MOSFET’s on-resis-
tance as the current-sensing element. Once the
high-side MOSFET turns off, the voltage across the low-
side MOSFET is monitored. If the voltage across the
low-side MOSFET (R DS(ON) x I INDUCTOR ) does not
exceed the current-limit threshold, the high-side MOS-
FET turns on normally at the start of the next cycle. If
count of N CL is cleared (see Figure 2). Hiccup mode
protects against continuous output short circuit.
Thermal-Overload Protection
The MAX5951 features an integrated thermal-overload
protection with temperature hysteresis. Thermal-over-
load protection limits the total power dissipation in the
device and protects it in the event of an extended ther-
mal fault condition. When the die temperature exceeds
+135°C, an internal thermal sensor shuts down the
device, turning off the power MOSFETs and allowing
the die to cool. After the die temperature falls by
+15°C, the part restarts with a soft-start sequence.
PWM Controller Design
Procedures
Setting the Undervoltage Lockout
Connect an external resistive divider from IN to PUVLO
to AGND to override the internal PWM UVLO divider.
The rising threshold at PUVLO is set to 1.220V with
120mV hysteresis. First select the PUVLO to AGND
resistor (R2), then calculate the resistor from IN to
PUVLO (R1) using the following equation:
R 1 = R 2 × ?
? 1 ?
the voltage across the low-side MOSFET exceeds the
current-limit threshold just before the beginning of a
new PWM cycle, the controller skips that cycle. During
severe overload or short-circuit conditions, the switch-
?
?
V IN
V PUVLO
?
?
ing frequency of the device appears to decrease
because the on-time of the low-side MOSFET extends
beyond a clock cycle.
If the current-limit threshold is exceeded for eight cumu-
lative clock cycles (N CL ), the device shuts down (both
DH and DL are pulled low) for 512 clock cycles (hiccup
timeout) and restarts with a soft-start sequence. If three
consecutive cycles pass without a current-limit event, the
where V IN is the input voltage at which the converter
needs to turn on, V PUVLO = 1.220V, and R2 is chosen
to be less than 20k ? . See Figure 3.
Leave PUVLO unconnected for the default PWM UVLO
threshold. In this case, an internal voltage-divider moni-
tors the supply voltage at IN and allows startup when
IN rises above 7V (typ).
IN
CURRENT LIMIT
IN
COUNT OF 8
N CL
INITIATE HICCUP
TIMEOUT
N HT
R1
CLR
PUVLO
IN
COUNT OF 3
N CLR
R2
CLR
Figure 2. Hiccup Block Diagram
Figure 3. External PWM UVLO Divider
14
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