参数资料
型号: MAX5951ETJ+T
厂商: Maxim Integrated Products
文件页数: 17/25页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1MHz
占空比: 88%
电源电压: 4.5 V ~ 16 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
12V/5V Input Buck PWM Controller
Compensation Design Guidelines
The MAX5951 uses a voltage-mode control scheme
that regulates the output voltage by comparing the
error amplifier output (COMP) with an internal ramp to
produce the required duty cycle. The output lowpass
LC filter creates a double pole at the resonant frequen-
cy, which has a gain drop of -40dB/decade. The com-
pensation network must compensate for this gain drop
and phase shift in order to achieve a stable closed-loop
system.
The basic regulator loop consists of a power modulator,
an output feedback divider, and a voltage-error amplifi-
The switching frequency is programmable between
100kHz and 1000kHz by an external resistor at RT. The
crossover frequency (f C ), which is the frequency when
the closed-loop gain is equal to unity, should be set to
f SW / 10 or f GBW / 25, whichever is lower.
The error amplifier must provide a gain-and-phase
boost to compensate for the rapid gain-and-phase loss
from the LC double pole. This is accomplished by utiliz-
ing type 3 compensation (see Figures 5 and 6) that
introduces two zeros and three poles into the control
loop. The error amplifier has a low-frequency pole (f P1 )
at the origin; two zeros at:
er. The power modulator has a DC gain set by
V IN /V RAMP , with a double pole and a single zero set by
the output inductance (L), the output capacitance
f Z1 =
1
2 π × R 5 × C 7
G MOD ( DC ) =
f Z2 =
(C OUT ), and its equivalent series resistance (ESR).
Below are equations that define the power modulator:
V IN
V RAMP
and:
1
2 π × R 3 × C 6
and higher frequency poles at:
f LC =
1
2 π L × C OUT
f P2 =
1
2 π × R 6 × C 6
f ZESR =
1
2 π × C OUT × R ESR
and:
f P3 =
1
2 π × R 5 × C 8
C8
C8
R5
C7
R5
C7
V OUT
C6
R3
R6
V OUT
C6
R3
R6
R4
EA
COMP
R4
EA
COMP
REF
REF
GAIN
(dB)
CLOSED-LOOP
GAIN
GAIN
(dB)
CLOSED-LOOP
GAIN
EA
EA
GAIN
GAIN
f Z1 f Z2
f C
f P2 f P3
FREQUENCY
f Z1 f Z2
f P2
f C
f P3
FREQUENCY
Figure 5. Error-Amplifier Compensation Circuit (Closed-Loop
and Error-Amplifier Gain Plot) for Ceramic Capacitors
Figure 6. Error-Amplifier Compensation Circuit (Closed-Loop
and Error-Amplifier Gain Plot) for Higher ESR Output
Capacitors
______________________________________________________________________________________
17
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