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参数资料
| 型号： | MAX5951ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/25页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 32-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 88% |
| 电源电压： | 4.5 V ~ 16 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
12V/5V Input Buck PWM Controller
Internal Linear Regulator (REG)
REG is the output terminal of a 5V LDO, which is pow-
ered from IN and provides power to the IC. Bypass
REG to AGND with a 2.2μF ceramic capacitor. Place
the capacitor physically close to the MAX5951 to pro-
vide good bypassing. REG is intended for powering
only the internal circuitry and should not be used to
supply power to external loads.
Low-Side MOSFET Driver Supply (DREG)
DREG is the supply input for the low-side MOSFET dri-
ver. Connect DREG to REG externally. Adding an RC
filter (5 ? resistor and 2.2μF ceramic capacitor) from
REG to DREG filters out the high peak currents of the
MOSFET drivers.
High-Side MOSFET Driver Supply (BST)
BST supplies the power for the high-side MOSFET dri-
vers. Connect the bootstrap diode from BST to DREG
(anode at DREG and cathode at BST). Connect a boot-
strap 1μF ceramic capacitor between BST and LX.
MOSFET Gate Drivers (DH, DL)
The high-side (DH) and low-side (DL) drivers drive the
gates of the external n-channel MOSFETs. The drivers’
2A peak source-and-sink current capability provides
ample drive to ensure fast rise and fall times of the
switching MOSFETs. Short rise and fall times minimize
switching losses. For low output-voltage applications
where the duty cycle is less than 50%, choose a high-
side MOSFET (Q2) with a moderate R DS(ON) . Choose a
low-side MOSFET (Q1) with a very low R DS(ON) .
The gate driver circuitry also provides a break-before-
make time (25ns, typ) to prevent shoot-through currents
during transition.
Oscillator/Synchronization Input (SYNCIN)/
Synchronization Output (SYNCOUT)
Use an external resistor at RT to program the MAX5951
switching frequency from 100kHz to 1MHz.
Choose the appropriate resistor at RT to calculate the
desired output switching frequency (f SW ):
f SW (Hz) = (5 x 10 10 ) / R RT ( ? )
Connect an external clock (SYNCOUT from another
MAX5950 or MAX5951) at SYNCIN for external clock
synchronization. For proper synchronization, the exter-
nal frequency must be at least 20% higher than the
frequency programmed through the RT input. If
SYNCIN is 50% duty cycle, SYNCOUT is shifted by
180°, allowing the reduction of the DC-DC converter
input bypass capacitor.
SYNCOUT is a synchronization signal that is used to
drive the SYNCIN of a second MAX5950 or MAX5951.
Tracking (STARTUP)
The STARTUP input in conjunction with digital soft-start
provides simple ratiometric tracking. When using multi-
ple MAX5950s or MAX5951s, in addition to connecting
SYNCIN and SYNCOUT signals appropriately, connect
the STARTUP of all the devices together. STARTUP syn-
chonizes the soft-start of all the devices’ references, and
hence their respective output voltages track ratiometri-
cally. See Figure 1 and the Typical Operating Circuits .
The STARTUP input has an internal 10μA pullup cur-
rent, but can be driven by external logic. When using
multiple converters, connect the STARTUP of all the
devices together.
Startup Sequencing (DCENI, THRESH)
The DCENI input must be above V THRESH for the PWM
controller to start. By connecting the DCENI inputs of
multiple devices together and having different start
thresholds (V THRESH_ ), the startup of the PWM con-
trollers can be staggered to provide power sequenc-
ing. Connect a resistive divider from REG to THRESH to
AGND to set the start thresholds of each device.
Connect THRESH to AGND to produce a default
1.220V threshold for DCENI. See Figure 1 and the
Typical Operating Circuits.
Power-Good Sequencing (PGOOD, SENSE)
The PGOOD outputs and DCENI inputs can be daisy-
chained to generate power sequencing. The PGOOD
output is pulled high when the voltage at SENSE is
above V REF (800mV, typ). Connect a resistive divider
from the power-supply output voltage to SENSE to
AGND to set the power-good threshold. See Figure 1
and the Typical Operating Circuits.
12
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