参数资料
型号: MAX5951ETJ+T
厂商: Maxim Integrated Products
文件页数: 18/25页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1MHz
占空比: 88%
电源电压: 4.5 V ~ 16 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
12V/5V Input Buck PWM Controller
Compensation when f C < f ZESR
Figure 5 shows the error-amplifier feedback, as well as
its gain response for circuits that use low-ESR output
capacitors (ceramic). In this case, f C occurs before
f ZESR .
f Z1 is set to 0.5 x f LC and f Z2 is set to f LC in order to
compensate for the gain-and-phase loss due to the
double pole. Choose the inductor (L) and output
capacitor (C OUT ) as described in the Inductor
Selection and Output Capacitor Selection sections.
Pick a value for the feedback resistor R5 in Figure 5
(values between 1k ? and 10k ? are adequate). C7 is
then calculated as:
Compensation when f C > f ZESR
For larger ESR capacitors such as tantalum and alu-
minum electrolytic, f ZESR can occur before f C . If f C >
f ZESR , then f C occurs between f P2 and f P3 . f Z1 and f Z2
remain the same as before; however, f P2 is now set
equal to f ZESR . The output capacitor’s ESR zero fre-
quency is higher than f LC but lower than the closed-
loop crossover frequency. The equations that define
the error amplifier’s poles and zeros (f Z1 , f Z2 , f P1 , f P2 ,
and f P3 ) are the same as before. However, f P2 is now
lower than the closed-loop crossover frequency. Figure
5 shows the error-amplifier feedback, as well as its gain
response for circuits that use higher ESR output capac-
itors (tantalum, aluminum electrolytic, etc.).
C 7 =
1
2 π × 0 . 5 × f LC × R 5
Pick a value for feedback resistor R5 in Figure 5 (values
between 1k ? and 10k ? are adequate). C7 is then cal-
culated as:
f C occurs between f Z2 and f P2 . The circuit is imple-
mented with C7 >> C8 and R3 >> R6, in which case,
C 7 =
1
2 π × 0 . 5 × f LC × R 5
G MOD ( fC ) =
G MOD ( fC ) =
C 6 = C OUT
R 5 × G MOD ( DC )
R 3 ≈
C OUT × ESR
the error amplifier gain (G EA ) at f C is due primarily to
C6 and R5. Therefore:
G EA ( fc ) = 2 π × f C × C 6 × R 5
The modulator gain at f C is:
G MOD ( DC )
( 2 π ) 2 × L × C OUT × f C 2
Since G EA(fC) x G MOD(fC) = 1, C6 is calculated by:
f × L × C × 2 π
R 5 × G MOD ( DC )
R3 is then calculated as:
1
2 π × f LC × C 6
f P2 is set at 1/2 the switching frequency (f SW ). R6 is
then calculated by:
The circuit is implemented with C7 >> C8 and R3 >>
R6, in which case the error-amplifier gain between f P2
and f P3 is approximately equal to:
R5
R 6
The modulator gain at f C is:
G MOD ( DC )
( 2 π ) 2 × L × C OUT × f C 2
Since G EA(fC) x G MOD(fC) = 1, R6 can then be calculat-
ed as:
R 6 ≈
( 2 π ) 2 × L × C OUT × f C 2
f P2 is set to f ZESR . C6 is then calculated as:
C 6 =
R 6
R3 is then calculated as:
R 6 =
1
2 π × C 6 × 0 . 5 × f SW
R 3 ≈
1
2 π × f LC × C 6
C 8 =
C 8 =
f P3 is set at 5 x f C . Therefore, C8 is calculated as:
1
2 π × R 5 × 5 × f C
f P3 is set at 5 x f C . Therefore, C8 is calculated as:
1
2 π × R 5 × 5 × f C
18
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