参数资料
型号: MAX6852AEE+T
厂商: Maxim Integrated
文件页数: 13/32页
文件大小: 0K
描述: IC VFD CTRLR MATRIX 16QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
显示器类型: 真空荧光 (VF)
配置: 5 x 7(矩阵)
接口: 串行
电流 - 电源: 3.5mA
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
4-Wire Interfaced, 5 ? 7 Matrix Vacuum-
Fluorescent Display Controller
Control and Operation Using the 4-Wire
Interface
Table 7. Character Map
Controlling the MAX6852 requires sending a 16-bit
word. The first byte, D15 through D8, is the command
address, and the second byte, D7 through D0, is the
MSB
LSB
x000
x001
x010
x011
x100
x101
x110
x111
data to be written to the command address (Table 23).
0000
RAM00
RAM16
Connecting Multiple MAX6852s to the
4-Wire Bus
Daisy-chain multiple MAX6852s by connecting the
0001
RAM01
RAM17
DOUT of one device to the DIN of the next, and driving
SCLK and CS lines in parallel. Data at DIN propagates
through the internal shift registers and appears at
0010
RAM02
RAM18
DOUT 15.5 clock cycles later, clocked out on the rising
edge of SCLK. When sending commands to daisy-
chained MAX6852s, all devices are accessed at the
0011
RAM03
RAM19
same time. An access requires (16 x n) clock cycles,
where n is the number of MAX6852s connected togeth-
er. To update just one device in a daisy-chain, send the
0100
RAM04
RAM20
no-op command (0x00) to the others. Care must be
taken on power-up when daisy-chaining the serial inter-
face in this manner. Configure each MAX6852 ’ s PORT0
0101
RAM05
RAM21
or PORT1 outputs, in turn, to act as DOUT before data
propagates through it. For this reason, PORT0 is the
preferred output to configure as DOUT because its out-
0110
RAM06
RAM22
put on power-up is low. This means that a daisy-
chained DIN input taking data from an uninitialized
PORT0 output clocks in 16 logic zeros, which is the
0111
RAM07
RAM23
safe no-op instruction.
Writing Device Registers
The MAX6852 contains a 16-bit shift register into which
DIN is clocked on the rising edge of SCLK, when CS is
low. When CS is high, transitions on SCLK have no
effect. When CS goes high, the 16 bits in the shift regis-
ter are parallel loaded into a 16-bit latch. The 16 bits in
the latch are then decoded and executed.
The MAX6852 is written to using the following
sequence:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is low,
indicating a write command.
4) Take CS high (while SCLK is still high after clocking
in the last data bit).
5) Take SCLK low.
Figure 7 shows a write operation when 16 bits are
transmitted.
1000
1001
1010
1011
1100
1101
1110
1111
RAM08
RAM09
RAM10
RAM11
RAM12
RAM13
RAM14
RAM15
______________________________________________________________________________________
13
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