参数资料
| 型号： | MAX6852AEE+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 16/32页 |
| 文件大小： | 0K |
| 描述： | IC VFD CTRLR MATRIX 16QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 显示器类型： | 真空荧光 (VF) |
| 配置： | 5 x 7（矩阵） |
| 接口： | 串行 |
| 电流 - 电源： | 3.5mA |
| 电源电压： | 2.7 V ~ 3.6 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
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4-Wire Interfaced, 5 ? 7 Matrix Vacuum-
Fluorescent Display Controller
VFLOAD
t VCSW
t VCL
t VCH
t VCP
t VCSH
VFCLK
t VDS
VFDOUT
DD0
DD1
M-1
M (M IS VALUE IN SHIFT-LIMIT REGISTER)
Figure 9. VFD Interface Timing Diagram
ONE COMPLETE MULTIPLEX CYCLE AROUND N GRIDS (OSC = 4MHz)
START OF NEXT
CYCLE
100 μ s TIMESLOT
GRID 0
100 μ s TIMESLOT
GRID 1
100 μ s TIMESLOT
GRID N-4
100 μ s TIMESLOT
GRID N-3
100 μ s TIMESLOT
GRID N-2
100 μ s TIMESLOT
GRID N-1
100 μ s TIMESLOT
GRID 0
500ns 500ns 500ns 500ns
GRID 0's 100 μ s MULTIPLEX TIMESLOT
VFCLK
VFDOUT
DD0
DD1 DD2
DD3
DD4 DD5 DD6 DD7
DD8 DD9 DD10
M-4
M-3
M-2 M-1
M
(M IS VALUE IN SHIFT-LIMIT REGISTER)
GRID 1's DATA, SENT DURING GRID 0's TIMESLOT
VFLOAD
Figure 10. VFD Multiplex Timing Diagram
between grids. Thus, image ghosting is avoided. If a
display has very slow phosphor, then the allowed decay
time can be doubled by not using a 15/16 duty cycle.
VFBLANK Polarity Register
The VFBLANK polarity register sets the active level of
the VFBLANK output pin (Table 26).
No-Op Register
A write to the no-op register is ignored.
Display-Test and Device ID Register
Writing the display-test and device ID register switches
the drivers between one of two modes: normal and dis-
play test. Display-test mode turns all segments and
annunciators on and sets the duty cycle to 7/16 (half-
power) (Table 27).
Reading the display-test and device ID register returns
the MAX6852 device ID 0b0000 011 that identifies the
driver type, plus the display-test status in the LSB.
Output Shift-Limit Register
The output serial interface is used to transfer display
data from the MAX6852 to the display driver. The serial
interface bit-stream output length is programmable up
to 122 bits, which are labeled DD0 – DD121. Set the
number of bits with the shift-limit register, address
0x0E. If the shift-limit register is written with an out-of-
range value 0x7A to 0xFF, then the value 0x79 is stored
instead. Table 28 shows the shift-limit register.
Output Map
The output map comprises 122 words of 7-bit RAM.
The output map data should be written when the
MAX6852 is configured after power-up. Table 29 shows
the output map RAM codes.
16
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相关代理商/技术参数 |
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| MAX6853AEE | 功能描述:VFD驱动器 RoHS:否 制造商:Maxim Integrated 工作电源电压:8 V to 76 V, 3 V to 5.5 V 电源电流:0.9 mA, 700 uA 最大工作温度:+ 125 C 封装 / 箱体:SOIC-20 封装:Tube |
| MAX6853AEE+T | 功能描述:VFD驱动器 RoHS:否 制造商:Maxim Integrated 工作电源电压:8 V to 76 V, 3 V to 5.5 V 电源电流:0.9 mA, 700 uA 最大工作温度:+ 125 C 封装 / 箱体:SOIC-20 封装:Tube |
| MAX6853AEE-T | 功能描述:VFD驱动器 RoHS:否 制造商:Maxim Integrated 工作电源电压:8 V to 76 V, 3 V to 5.5 V 电源电流:0.9 mA, 700 uA 最大工作温度:+ 125 C 封装 / 箱体:SOIC-20 封装:Tube |
| MAX6854UK16D1+T | 功能描述:监控电路 Single nPower Supervisor RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX6854UK16D1-T | 功能描述:监控电路 RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
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